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1. 发明申请

WO2021096809A1 LOW POWER AND ROBUST LEVEL-SHIFTING PULSE LATCH FOR DUAL-POWER MEMORIES 审中-公开
公开(公告)号：WO2021096809A1
公开(公告)日：2021-05-20
申请号：PCT/US2020/059708
申请日：2020-11-09
申请人： QUALCOMM INCORPORATED
发明人： BHASKARAN, Adithya , SAHU, Rahul , GUPTA, Sharad Kumar
IPC分类号： G11C5/14 , G11C7/10
摘要： A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory -power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.

2. 发明申请

WO2020185469A1 IMPROVED ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL 审中-公开
公开(公告)号：WO2020185469A1
公开(公告)日：2020-09-17
申请号：PCT/US2020/021015
申请日：2020-03-04
申请人： QUALCOMM INCORPORATED
发明人： RAJ, Pradeep , SAHU, Rahul , GUPTA, Sharad Kumar
IPC分类号： G11C8/08 , G11C7/22 , G11C8/18 , G11C11/413 , G11C11/418
摘要： Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

3. 发明申请

WO2023278173A1 MEMORY WITH SCAN CHAIN TESTING OF COLUMN REDUNDANCY LOGIC AND MULTIPLEXING 审中-公开
公开(公告)号：WO2023278173A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/033887
申请日：2022-06-16
申请人： QUALCOMM INCORPORATED
发明人： SAHU, Rahul , GUPTA, Sharad Kumar , KIM, Jung Pill , JUNG, Chulmin , ABRAHAM, Jais
IPC分类号： G11C29/02 , G11C29/00 , G11C29/24 , G11C29/32 , G11C29/12 , G11C29/46 , G11C2029/1204 , G11C2029/3202 , G11C29/024 , G11C29/10 , G11C29/781 , G11C29/848 , G11C7/06 , G11C7/106 , G11C7/1096
摘要： A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

4. 发明申请

WO2017172150A1 WORDLINE ADJUSTMENT SCHEME 审中-公开
标题翻译： WORDLINE调整计划
公开(公告)号：WO2017172150A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/019488
申请日：2017-02-24
申请人： QUALCOMM INCORPORATED
发明人： SAHU, Rahul , GUPTA, Sharad Kumar
IPC分类号： G11C8/08 , G11C11/413 , G11C11/418
CPC分类号： G11C11/419 , G11C8/08 , G11C11/412 , G11C11/413 , G11C11/418 , G11C16/08 , G11C16/30
摘要： A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.
摘要翻译：提供了一种用于操作存储器的存储器和方法。存储器包括具有晶体管的存储器单元和输出耦合到存储器单元的字线的字线驱动器。字线驱动器调整字线的电压电平以补偿晶体管的参数。该方法包括断言字线电压以访问具有晶体管的存储器单元并且调整字线电压以补偿晶体管的参数。提供另一个内存。存储器包括存储器单元和输出耦合到存储器单元的字线的字线驱动器。字线驱动器基于字线的反馈来调整字线的电压电平。

5. 发明授权

EP3437098B1 WORDLINE ADJUSTMENT SCHEME 有权
公开(公告)号：EP3437098B1
公开(公告)日：2019-07-24
申请号：EP17709316.8
申请日：2017-02-24
申请人： Qualcomm Incorporated
发明人： SAHU, Rahul , GUPTA, Sharad Kumar
IPC分类号： G11C8/08 , G11C11/413 , G11C11/418 , G11C11/412

6. 发明申请

WO2023080996A1 MEMORY WITH EFFICIENT DYNAMIC VOLTAGE STRESS SCAN CONTROLLED BY ASYNCHRONOUS INPUTS 审中-公开
公开(公告)号：WO2023080996A1
公开(公告)日：2023-05-11
申请号：PCT/US2022/046341
申请日：2022-10-11
申请人： QUALCOMM INCORPORATED
发明人： RAJ, Pradeep , SAHU, Rahul , GUPTA, Sharad Kumar , JUNG, Chulmin
IPC分类号： G11C29/02
摘要： A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

7. 发明申请

WO2018052697A1 ARCHITECTURE TO IMPROVE WRITE-ABILITY IN SRAM 审中-公开
标题翻译：改善SRAM写入能力的架构
公开(公告)号：WO2018052697A1
公开(公告)日：2018-03-22
申请号：PCT/US2017/048920
申请日：2017-08-28
申请人： QUALCOMM INCORPORATED
发明人： RAJ, Pradeep , GUPTA, Sharad Kumar , SAHU, Rahul , HOLLA VAKWADI, Lakshmikantha
IPC分类号： G11C11/419 , G11C5/02 , G11C5/14
CPC分类号： G11C11/419 , G11C5/025 , G11C5/14
摘要： A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.
摘要翻译：公开了一种存储器和设备。存储器包括具有多个存储器单元的存储器核心。存储器还包括第一写入辅助电路，其被配置为辅助写入存储器核心的多个存储器单元的第一组。另外，存储器包括第二写入辅助电路，其被配置为辅助写入存储器核心的多个存储器单元的第二组。该设备包括至少一个处理器。该装置还包括存储器阵列。存储器阵列包括具有多个存储器单元的存储器核心。存储器还包括第一写入辅助电路和第二写入辅助电路，第一写入辅助电路被配置为辅助写入存储器核心的多个存储器单元的第一组，第二写入辅助电路被配置为辅助写入存储器的多个存储器单元的第二组芯

8. 发明申请

WO2017053068A1 ADAPTIVE NEGATIVE BIT LINE WRITE ASSIST 审中-公开
标题翻译：自适应负号线写入辅助
公开(公告)号：WO2017053068A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/050577
申请日：2016-09-07
申请人： QUALCOMM INCORPORATED
发明人： SAHU, Rahul
IPC分类号： G11C11/419 , G11C7/12 , G11C7/14
CPC分类号： G11C11/419 , G11C5/145 , G11C7/12 , G11C7/14
摘要： SRAM with a write assist circuit that responds to an indication that a write operation on a modeled memory cell is successful by releasing a negative bit line boost. The write assist circuit comprises a capacitance, of which one terminal is connected to a discharged bit line during a write operation and of which the other terminal is floated to terminate a negative bit line boost on completion of a write operation to the modeled memory cell.
摘要翻译：具有写辅助电路的SRAM，其通过释放负位线提升来响应对建模的存储器单元的写操作成功的指示。写辅助电路包括一个电容，其中一个端子在写入操作期间连接到一个放电的位线，并且另一个端子被浮置以在对所建模的存储器单元的写入操作完成时终止负位线升压。

9. 发明公开

EP4143666A1 POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT 审中-实审
公开(公告)号：EP4143666A1
公开(公告)日：2023-03-08
申请号：EP21726783.0
申请日：2021-04-29
申请人： QUALCOMM INCORPORATED
发明人： RAJ, Pradeep , SAHU, Rahul , GUPTA, Sharad Kumar , JUNG, Chulmin
IPC分类号： G06F1/3287 , G06F1/26 , H03K19/00

10. 发明授权

EP3353790B1 ADAPTIVE NEGATIVE BIT LINE WRITE ASSIST 有权
公开(公告)号：EP3353790B1
公开(公告)日：2020-03-04
申请号：EP16766445.7
申请日：2016-09-07
申请人： Qualcomm Incorporated
发明人： SAHU, Rahul
IPC分类号： G11C11/419 , G11C7/12 , G11C7/14

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