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1. 发明申请

WO2012149303A1 MULTIPLE SLIMBUS CONTROLLERS FOR SLIMBUS COMPONENTS 审中-公开
标题翻译： SLIMBUS组件的多个SLIMBUS控制器
公开(公告)号：WO2012149303A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/035436
申请日：2012-04-27
申请人： QUALCOMM INCORPORATED , GRUBER, Hans Georg , ARCEO, Julio , HARIHARAN, Magesh , MOHAN, Suren , LANDGUTH, Mark A.
发明人： GRUBER, Hans Georg , ARCEO, Julio , HARIHARAN, Magesh , MOHAN, Suren , LANDGUTH, Mark A.
IPC分类号： H04L12/46 , H04L12/66
CPC分类号： H04L12/40013
摘要： Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.
摘要翻译：呈现用于控制连接到数据总线和/或以其他方式与数据总线相关的组件的方法，系统，装置和计算机可读介质。根据本公开的一个或多个方面，可以识别具有数据总线管理能力的多个处理设备和与多个处理设备相关联的至少一个数据总线。随后，可以通过由至少一个数据总线使用的消息传递层来建立用于在多个处理设备和至少一个数据总线之间通信的处理器间通信（IPC）层。然后可以使用多个处理设备中的至少一个通过IPC层来控制与至少一个数据总线相关联的至少一个组件。

2. 发明申请

WO2012149298A1 WAKING A MEDIA BUS 审中-公开
标题翻译：调用媒体总线
公开(公告)号：WO2012149298A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/035428
申请日：2012-04-27
申请人： QUALCOMM INCORPORATED , GRUBER, Hans Georg , ARCEO, Julio , HARIHARAN, Magesh , MOHAN, Suren
发明人： GRUBER, Hans Georg , ARCEO, Julio , HARIHARAN, Magesh , MOHAN, Suren
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06F1/04 , G06F11/0763 , G06F11/1658
摘要： Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.
摘要翻译：介绍了在串行低功耗芯片间媒体总线（SLIMbus）上重新启动数据传输的安排。可以以活动模式将时钟信号提供给与SLIMbus通信耦合的组件。紧接在提供处于活动模式的时钟信号之前，时钟信号可能已经处于暂停模式。至少在时钟信号处于激活模式之前，时钟信号处于暂停模式，数据线可能已经不工作（例如，数据线上的切换可能不存在）。可以发送帧的帧同步数据。由组件接收的帧的帧同步数据可能不匹配预期的帧同步数据。有效负载数据可以作为帧的一部分被发送到组件，其中预期有效载荷数据被组件正确地读取。

3. 发明申请

WO2023004570A1 ACTIVATION BUFFER ARCHITECTURE FOR DATA-REUSE IN A NEURAL NETWORK ACCELERATOR 审中-公开
公开(公告)号：WO2023004570A1
公开(公告)日：2023-02-02
申请号：PCT/CN2021/108594
申请日：2021-07-27
申请人： QUALCOMM INCORPORATED , WADHWA, Sameer , MOHAN, Suren , ZHU, Peiyu , LI, Ren , SRIVASTAVA, Ankit , MIRHAJ, Seyed Arash
发明人： WADHWA, Sameer , MOHAN, Suren , ZHU, Peiyu , LI, Ren , SRIVASTAVA, Ankit , MIRHAJ, Seyed Arash
IPC分类号： G06N3/04 , G06N3/063
摘要： Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes computation circuitry configured to perform a convolution operation, the computation circuitry having multiple input rows, and an activation buffer having multiple buffer segments coupled to the multiple input rows of the computation circuitry, respectively. In some aspects, each of the multiple buffer segments comprises a first multiplexer having a plurality of multiplexer inputs, and each of the plurality of multiplexer inputs of one of the first multiplexers on one of the multiple buffer segments is coupled to a data output of the activation buffer on another one of the multiple buffer segments.

4. 发明公开

EP4396699A1 CONFIGURABLE NONLINEAR ACTIVATION FUNCTION CIRCUITS 审中-公开
公开(公告)号：EP4396699A1
公开(公告)日：2024-07-10
申请号：EP22769057.5
申请日：2022-08-22
申请人： Qualcomm Incorporated
发明人： MOHAN, Suren , LI, Ren , KULKARNI, Prajakt , LAMB, Aaron Douglass
IPC分类号： G06F17/17 , G06N3/04 , G06N3/063
CPC分类号： G06N3/063 , G06F17/17 , G06N3/048 , G06F7/544

5. 发明授权

EP2791810B1 SYSTEM AND METHOD OF SENDING DATA VIA A PLURALITY OF DATA LINES ON A BUS 有权
标题翻译：系统和方法用于发送数据的多个数据线路上的总线
公开(公告)号：EP2791810B1
公开(公告)日：2016-11-16
申请号：EP12812774.3
申请日：2012-12-14
申请人： Qualcomm Incorporated
发明人： GRUBER, Hans Georg , HARIHARAN, Magesh , ARCEO, Julio , MOHAN, Suren , BALATSOS, Aris
IPC分类号： G06F13/42
CPC分类号： H04L47/726 , G06F13/423 , G06F13/4291
摘要： A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.

6. 发明申请

WO2023044303A1 ELIMINATING MEMORY BOTTLENECKS FOR DEPTHWISE CONVOLUTIONS 审中-公开
公开(公告)号：WO2023044303A1
公开(公告)日：2023-03-23
申请号：PCT/US2022/076357
申请日：2022-09-13
申请人： QUALCOMM INCORPORATED
发明人： WADHWA, Sameer , MOHAN, Suren , LI, Ren , SRIVASTAVA, Ankit , MIRHAJ, Seyed Arash , SHEN, Jian
IPC分类号： G06N3/04 , G06N3/063 , G06F7/544 , G06F17/15 , G06F15/78
摘要： Certain aspects of the present disclosure provide techniques for efficient depthwise convolution. A convolution is performed with a compute-in-memory (CIM) array to generate CIM output, and at least a portion of the CIM output corresponding to a first output data channel, of a plurality of output data channels in the CIM output, is written to a digital multiply-accumulate (DMAC) activation buffer. A patch of the CIM output is read from the DMAC activation buffer, and weight data is read from a DMAC weight buffer. Multiply-accumulate (MAC) operations are performed with the patch of CIM output and the weight data to generate a DMAC output.

7. 发明申请

WO2023034698A1 CONFIGURABLE NONLINEAR ACTIVATION FUNCTION CIRCUITS 审中-公开
公开(公告)号：WO2023034698A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/075270
申请日：2022-08-22
申请人： QUALCOMM INCORPORATED
发明人： MOHAN, Suren , LI, Ren , KULKARNI, Prajakt , LAMB, Aaron Douglass
IPC分类号： G06F17/17 , G06N3/04 , G06N3/063
摘要： Certain aspects of the present disclosure provide a processor, comprising: a configurable nonlinear activation function circuit configured to: determine, based on a selected nonlinear activation function, a set of parameters for the nonlinear activation function; and generate output data based on application of the set of parameters for the nonlinear activation function, wherein: the configurable nonlinear activation function circuit comprises at least one nonlinear approximator comprising at least two successive linear approximators, and each linear approximator of the at least two successive linear approximators is configured to approximate a linear function using one or more function parameters of the set of parameters.

8. 发明申请

WO2022197534A1 COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION 审中-公开
公开(公告)号：WO2022197534A1
公开(公告)日：2022-09-22
申请号：PCT/US2022/019856
申请日：2022-03-10
申请人： QUALCOMM INCORPORATED
发明人： MIRHAJ, Seyed Arash , SRIVASTAVA, Ankit , WADHWA, Sameer , LI, Ren , MOHAN, Suren
IPC分类号： G11C11/54 , G06N3/063 , G11C7/10 , G11C11/412 , G11C11/418 , G11C11/419
摘要： A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

9. 发明申请

WO2013090752A1 SYSTEM AND METHOD OF SENDING DATA VIA A PLURALITY OF DATA LINES ON A BUS 审中-公开
标题翻译：通过数据线在总线上发送数据的系统和方法
公开(公告)号：WO2013090752A1
公开(公告)日：2013-06-20
申请号：PCT/US2012/069800
申请日：2012-12-14
申请人： QUALCOMM INCORPORATED
发明人： GRUBER, Hans Georg , HARIHARAN, Magesh , ARCEO, Julio , MOHAN, Suren , BALATSOS, Aris
IPC分类号： G06F13/42
CPC分类号： H04L47/726 , G06F13/423 , G06F13/4291
摘要： A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.
摘要翻译：一种方法包括将数据从第一串行低功率芯片间媒体总线（SLIMbus）组件发送到第二SLIMbus组件。该方法还包括经由多个SLIMbus数据线的至少第一SLIMbus数据线发送数据。

10. 发明申请

WO2012149311A1 NON-PORTED GENERIC DEVICE (SOFTWARE MANAGED GENERIC DEVICE) 审中-公开
标题翻译：非定制通用设备（软件管理的一般设备）
公开(公告)号：WO2012149311A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/035446
申请日：2012-04-27
申请人： QUALCOMM INCORPORATED , GRUBER, Hans Georg , ARCEO, Julio , HARIHARAN, Magesh , MOHAN, Suren , LANDGUTH, Mark A.
发明人： GRUBER, Hans Georg , ARCEO, Julio , HARIHARAN, Magesh , MOHAN, Suren , LANDGUTH, Mark A.
IPC分类号： G06F13/42
CPC分类号： G06F13/4291
摘要： Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.
摘要翻译：公开了利用非移植通用设备（NGD）或其他非端口硬件将处理设备耦合到访问串行数据总线上的组件而不需要集成管理器硬件的技术。使用NGD，处理设备可以利用串行数据总线上的可用未使用的带宽与与串行数据总线耦合的组件进行通信，包括具有管理器硬件的处理设备。公开了各种改变和实施例。

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