专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2015006231A1 METHOD AND DEVICE FOR ESTIMATING DAMAGE TO MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENTS 审中-公开
标题翻译：用于估计对磁性隧道结（MTJ）元件的损伤的方法和装置
公开(公告)号：WO2015006231A1
公开(公告)日：2015-01-15
申请号：PCT/US2014/045602
申请日：2014-07-07
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , ZHU, Xiaochun , KANG, Seung H.
IPC分类号： G11B5/31 , G11C29/50
CPC分类号： G01R31/26 , G11B5/3166 , G11C11/16 , G11C29/50 , G11C2029/5002
摘要： For first and second magnetic tunnel junction (MTJ) elements, a trend in a relationship between an electrical characteristic of the first and second MTJ elements and an area of the first and second MTJ elements may be determined. Damage to a sidewall of the first and second MTJ elements may be estimated from the trend. At least one operating parameter of an MTJ manufacturing apparatus may be modified based on an X or Y intercept a trend line.
摘要翻译：对于第一和第二磁性隧道结（MTJ）元件，可以确定第一和第二MTJ元件的电特性与第一和第二MTJ元件的面积之间的关系的趋势。可以从趋势估计对第一和第二MTJ元件的侧壁的损坏。可以基于X或Y拦截趋势线来修改MTJ制造装置的至少一个操作参数。

2. 发明申请

WO2014062705A1 MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR 审中-公开
标题翻译：基于磁性隧道结的随机数发生器
公开(公告)号：WO2014062705A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/065091
申请日：2013-10-15
申请人： QUALCOMM INCORPORATED
发明人： LEE, Kangho , KIM, Taehyun , ZHU, Xiaochun , JACOBSON, David M. , MADALA, Raghu Sagar , WU, Wenqing , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： A random number generator system that utilizes a magnetic tunnel junction (MTJ) that is controlled by an STT-MTJ entropy controller that determines whether to proceed with generating random numbers or not by monitoring the health of the MTJ-based random number generator is illustrated. If the health of the random number generation is above a threshold, the STT-MTJ entropy controller shuts down the MTJ-based random number generator and sends a message to a requesting chipset that a secure key generation is not possible. If the health of the random number generation is below a threshold, the entropy controller allows the MTJ-based random number generator to generate random numbers based on a specified algorithm, the output of which is post processed and used by a cryptographic-quality deterministic random bit generator to generate a security key for a requesting chipset.
摘要翻译：示出了利用由STT-MTJ熵控制器控制的磁隧道结（MTJ）的随机数发生器系统，其通过监测基于MTJ的随机数发生器的健康来确定是否继续生成随机数。如果随机数生成的健康状况高于阈值，则STT-MTJ熵控制器关闭基于MTJ的随机数生成器，并且向请求芯片组发送消息，即不可能产生安全密钥。如果随机数生成的健康状况低于阈值，则熵控制器允许基于MTJ的随机数发生器基于指定的算法产生随机数，其输出被后处理并由加密质量确定性随机使用以产生请求芯片组的安全密钥。

3. 发明申请

WO2014039573A1 MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR 审中-公开
标题翻译：基于磁性隧道结的随机数发生器
公开(公告)号：WO2014039573A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/058083
申请日：2013-09-04
申请人： QUALCOMM INCORPORATED
发明人： ZHU, Xiaochu , WU, Wenqing , JACOBSON, David M. , KANG, Seung H. , YUEN, Kendrick H.
IPC分类号： G06F7/58
CPC分类号： G06F7/582 , G06F7/588
摘要： Embodiments of the disclosure are directed to generating a random number. An embodiment of the disclosure passes a current (210; 510; 610; 1010) from a read operation (202; 502; 602; 1002) through a magnetic tunnel junction (MTJ) (200; 500; 600; 700a; 700b; 1000) to cause a first magnetization orientation of a free layer (204; 504; 604; 704; 1004) to switch to a second magnetization orientation, the switch in magnetization orientation causing a change in a resistance of the MTJ, and periodically samples the resistance of the MTJ to generate a bit value for the random number.
摘要翻译：本公开的实施例涉及生成随机数。本公开的一个实施例将来自读取操作（202; 502; 602; 1002）的电流（210; 510; 610; 1010）通过磁性隧道结（MTJ）（200; 500; 600; 700a; 700b; 1000 ）引起自由层（204; 504; 604; 704; 1004）的第一磁化取向切换到第二磁化取向，磁化方向上的开关引起MTJ的电阻的变化，并周期性地对电阻进行采样的MTJ来生成随机数的位值。

4. 发明申请

WO2014039565A1 LOW COST PROGRAMMABLE MULTI-STATE DEVICE 审中-公开
标题翻译：低成本可编程多状态器件
公开(公告)号：WO2014039565A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/058075
申请日：2013-09-04
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , KANG, Seung H.
IPC分类号： H01L23/525 , H01L27/22 , H01L43/08 , H01L43/12
CPC分类号： G11C17/02 , G11C11/005 , G11C11/5607 , G11C11/5692 , G11C17/00 , G11C17/14 , G11C17/16 , G11C17/165 , H01L23/5252 , H01L23/5256 , H01L27/22 , H01L27/224 , H01L43/08 , H01L43/12 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a preprogrammed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metalinsulator- metal (MIM) capacitor structure.
摘要翻译：仅使用一个，两个或三个掩模，在后端（BEOL）过程中构造了一次性可编程（OPT）和多时间可编程（MTP）结构。 OTP / MTP结构可以编程为三种状态之一，预编程高电阻状态，可编程低电阻状态和可编程非常高电阻状态。在可编程低电阻状态下，在抗熔丝编程期间阻挡层被分解，使得OTP / MTP结构呈现出百欧姆量级的电阻。在非常高的电阻状态下，在编程期间导通熔丝被断开，使得OTP / MTP结构呈现以兆欧姆数量级的电阻。 OTP / MTP结构可以包括磁隧道结（MTJ）结构或金属绝缘体金属（MIM）电容器结构。

5. 发明申请

WO2013112615A1 MULTI-BIT MAGNETIC TUNNEL JUNCTION MEMORY AND METHOD OF FORMING SAME 审中-公开
标题翻译：多位磁铁隧道结内存及其形成方法
公开(公告)号：WO2013112615A1
公开(公告)日：2013-08-01
申请号：PCT/US2013/022789
申请日：2013-01-23
申请人： QUALCOMM INCORPORATED
发明人： WU, Wenqing , LI, Sean , ZHU, Xiaochun , MADALA, Raghu Sagar , KANG, Seung H. , YUEN, Kendrick H.
IPC分类号： G11C11/15 , G11C11/16 , H01L43/08 , H01L43/12
CPC分类号： G11C11/161 , G11C11/1659 , G11C11/5607 , H01L43/08
摘要： A spin-torque transfer (STT) magnetic tunnel junction (MTJ) memory includes a unitary fixed magnetic layer, a magnetic barrier layer on the unitary fixed magnetic layer, a free magnetic layer having a plurality of free magnetic islands on the magnetic barrier layer, and a cap layer overlying the free magnetic layer. Also a method of forming an STT-MTJ memory.
摘要翻译：自旋转矩传递（STT）磁性隧道结（MTJ）存储器包括整体固定磁性层，整体固定磁性层上的磁性阻挡层，在磁性阻挡层上具有多个自由磁性岛的自由磁性层，以及覆盖自由磁性层的覆盖层。也是形成STT-MTJ存储器的方法。

6. 发明申请

WO2013049186A1 PROGRAMMABLE LOGIC SENSING IN MAGNETIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：磁性随机访问存储器中的可编程逻辑感测
公开(公告)号：WO2013049186A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/057310
申请日：2012-09-26
申请人： QUALCOMM INCORPORATED , KIM, Jung Pill , KIM, Tae Hyun , WU, Wenqing , ZHU, Xiaochun , KANG, Seung H.
发明人： KIM, Jung Pill , KIM, Tae Hyun , WU, Wenqing , ZHU, Xiaochun , KANG, Seung H.
IPC分类号： G11C11/16 , H03K19/20 , H03K19/173 , G11C13/00
CPC分类号： G11C11/16 , G11C13/0069 , H03K19/02 , H03K19/20
摘要： A Magnetic Random Access Memory (MRAM) logic circuit (302) includes read sensing circuitry (208, 300) having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry (302) may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.
摘要翻译：磁性随机存取存储器（MRAM）逻辑电路（302）包括读取感测电路（208,300），其具有对应于第一类逻辑电路的第一电平和对应于第二类逻辑电路的第二逻辑电平。逻辑电路（302）可以根据正在实现的逻辑电路的类别在具有第一逻辑电平的电路和具有第二逻辑电平的电路之间切换。

7. 发明申请

WO2013040069A1 SYMMETRICALLY SWITCHABLE SPIN-TRANSFER-TORQUE MAGNETORESISTIVE DEVICE 审中-公开
标题翻译：对称可转换转子 - 转矩磁阻器件
公开(公告)号：WO2013040069A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054911
申请日：2012-09-12
申请人： QUALCOMM Incorporated , CHEN, Wei-Chuan , LEE, Kangho , ZHU, Xiaochun , KANG, Seung H.
发明人： CHEN, Wei-Chuan , LEE, Kangho , ZHU, Xiaochun , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C11/161
摘要： A spin transfer torque magnetic random access memory (STT-MRAM) device includes magnetic tunnel junctions (MTJs) with reduced switching current asymmetry At least one switching asymmetry balance layer (SABL, 112) near the free layer (108) of the MTJ reduces a first switching current lc(p-ap) causing the value of the first switching current to be nearly equal to the value of a second switching current lc(ap-p) without increasing the average switching current of the device. The SABL (112) may be a non-magnetic switching asymmetry balance layer (NM-SABL, 110) and/or a magnetic switching asymmetry balance layer (M-SABL, 112).
摘要翻译：自旋传递转矩磁随机存取存储器（STT-MRAM）装置包括具有降低的开关电流不对称性的磁隧道结（MTJ）。在MTJ的自由层（108）附近的至少一个开关不对称平衡层（SABL，112）减少了第一开关电流lc（p-ap）使得第一开关电流的值几乎等于第二开关电流lc（ap-p）的值，而不增加器件的平均开关电流。 SABL（112）可以是非磁性开关不对称平衡层（NM-SABL，110）和/或磁性开关不对称平衡层（M-SABL，112）。

8. 发明申请

WO2012015754A3 LATCHING CIRCUIT 审中-公开
公开(公告)号：WO2012015754A3
公开(公告)日：2012-02-02
申请号：PCT/US2011/045222
申请日：2011-07-25
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , RYU, Kyungho , KIM, Jisu , KIM, Jung Pill , KANG, Seung H.
发明人： JUNG, Seong-Ook , RYU, Kyungho , KIM, Jisu , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C7/06 , G11C7/20 , G11C11/16 , G11C14/00
摘要： A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.

9. 发明申请

WO2010080629A1 BALANCING A SIGNAL MARGIN OF A RESISTANCE BASED MEMORY CIRCUIT 审中-公开
标题翻译：平衡基于电阻的信号电路的信号
公开(公告)号：WO2010080629A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/068799
申请日：2009-12-18
申请人： QUALCOMM Incorporated , JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H. , YOON, Sei Seung , SANI, Mehdi Hamidi
发明人： JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H. , YOON, Sei Seung , SANI, Mehdi Hamidi
IPC分类号： G11C11/16 , G11C7/06
CPC分类号： G11C7/14 , G11C7/12 , G11C11/1673
摘要： A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.
摘要翻译：公开了一种基于电阻的存储器电路。电路包括数据单元的第一晶体管负载和适于检测第一逻辑状态的位线。位线耦合到第一晶体管负载并耦合到具有磁隧道结（MTJ）结构的数据单元。当位线具有第一电压值时，位线适于检测具有逻辑1值的数据，并且当位线具有第二电压值时，检测具有逻辑零值的数据。电路还包括参考单元的第二晶体管负载。第二晶体管负载耦合到第一晶体管负载，并且第二晶体管负载具有相关联的参考电压值。诸如晶体管宽度的第一晶体管负载的特性是可调节的，以修改第一电压值和第二电压值，而基本上不改变参考电压值。

10. 发明申请

WO2010036581A1 MAGNETIC ELEMENT UTILIZING PROTECTIVE SIDEWALL PASSIVATION 审中-公开
标题翻译：磁性元件利用防护性小型化
公开(公告)号：WO2010036581A1
公开(公告)日：2010-04-01
申请号：PCT/US2009/057523
申请日：2009-09-18
申请人： QUALCOMM Incorporated , KANG, Seung H. , YOON, Sei Seung
发明人： KANG, Seung H. , YOON, Sei Seung
IPC分类号： H01L43/08
CPC分类号： G01R33/098 , H01L43/08
摘要： Exemplary embodiments of the invention are directed to magnetic elements including a passivation layer for isolation from other on-chip elements. One embodiment is directed to an apparatus comprising a magnetic tunnel junction (MTJ) element. The MTJ element comprises: a first ferromagnetic layer; a second ferromagnetic layer; an insulating layer disposed between the first and second ferromagnetic layers; and an MTJ passivation layer forming protective sidewalls disposed adjacent to the first ferromagnetic layer, the second ferromagnetic layer, and the insulating layer.
摘要翻译：本发明的示例性实施例涉及包括用于与其它片上元件隔离的钝化层的磁性元件。一个实施例涉及一种包括磁性隧道结（MTJ）元件的装置。 MTJ元件包括：第一铁磁层; 第二铁磁层; 设置在所述第一和第二铁磁层之间的绝缘层; 以及形成与第一铁磁层，第二铁磁层和绝缘层相邻设置的保护侧壁的MTJ钝化层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式