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1. 发明申请

WO2014031129A1 SYSTEMS AND METHODS OF DATA EXTRACTION IN A VECTOR PROCESSOR 审中-公开
标题翻译：在矢量处理器中数据提取的系统和方法
公开(公告)号：WO2014031129A1
公开(公告)日：2014-02-27
申请号：PCT/US2012/052328
申请日：2012-08-24
申请人： QUALCOMM INCORPORATED , FRIDMAN, Jose , INGLE, Ajay Anant , MATHEW, Deepak , HOFFMAN, Marc, M. , LOPEZ, Michael, John
发明人： FRIDMAN, Jose , INGLE, Ajay Anant , MATHEW, Deepak , HOFFMAN, Marc, M. , LOPEZ, Michael, John
IPC分类号： G06F9/30 , G06F15/80
CPC分类号： G06F15/8084 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.
摘要翻译：公开了一种向量处理器中数据提取的系统和方法。在特定实施例中，向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，以及将重新排序的数据元素从目的寄存器复制到存储器。

2. 发明申请

WO2018022191A2 SYSTEM AND METHOD FOR PIECEWISE LINEAR APPROXIMATION 审中-公开
标题翻译：分块线性近似的系统和方法
公开(公告)号：WO2018022191A2
公开(公告)日：2018-02-01
申请号：PCT/US2017/035803
申请日：2017-06-02
申请人： QUALCOMM INCORPORATED
发明人： MATHEW, Deepak , INGLE, Ajay Anant , SUN, Yurong , ZHU, Jianming , HOFFMAN, Marc
IPC分类号： G06F17/17
摘要： An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.
摘要翻译：一种装置包括被配置为存储输入值的向量的一个或多个寄存器。该装置还包括系数确定单元，被配置为响应于单个指令的处理器的执行，选择多个分段分析系数。多个分段分析系数包括一组或多组分段分析系数，并且每组分段分析系数对应于输入值的向量的输入值。该装置进一步包括算术逻辑电路，该算术逻辑电路被配置为响应于至少单个指令的执行，基于多个分段分析系数和输入值向量来确定函数的估计输出值。

3. 发明申请

WO2013086060A1 SELECTIVE ACCESS OF A STORE BUFFER BASED ON CACHE STATE 审中-公开
标题翻译：基于缓存状态的存储缓冲区的选择性访问
公开(公告)号：WO2013086060A1
公开(公告)日：2013-06-13
申请号：PCT/US2012/068050
申请日：2012-12-05
申请人： QUALCOMM INCORPORATED
发明人： INGLE, Ajay Anant , CODRESCU, Lucian
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F2212/1028 , Y02D10/13
摘要： An apparatus includes a cache memory that includes a state array configured to store state information. The state information includes a state that indicates updated corresponding to a particular address of the cache memory is not stored in the cache memory but is available from at least one of multiple sources external to the cache memory, where at least one of the multiple sources is a store buffer.
摘要翻译：一种装置包括高速缓冲存储器，其包括配置为存储状态信息的状态阵列。状态信息包括指示与高速缓冲存储器的特定地址对应的更新的状态未被存储在高速缓冲存储器中，但是可以从高速缓冲存储器外部的多个源中的至少一个获得，其中多个源中的至少一个是一个商店缓冲区。

4. 发明申请

WO2013049765A1 FIFO LOAD INSTRUCTION 审中-公开
标题翻译： FIFO加载指令
公开(公告)号：WO2013049765A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/058181
申请日：2012-09-30
申请人： QUALCOMM INCORPORATED , ZENG, Mao , CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant
发明人： ZENG, Mao , CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30043
摘要： An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.
摘要翻译：指令识别寄存器和存储器位置。在由处理器执行指令时，从存储器位置加载一个物品，并执行移位和插入操作以移位寄存器中的数据并将该项目插入到寄存器中。

5. 发明申请

WO2009032936A1 SYSTEM AND METHOD OF EXECUTING INSTRUCTIONS IN A MULTI-STAGE DATA PROCESSING PIPELINE 审中-公开
标题翻译：在多级数据处理管道中执行指令的系统和方法
公开(公告)号：WO2009032936A1
公开(公告)日：2009-03-12
申请号：PCT/US2008/075270
申请日：2008-09-04
申请人： QUALCOMM Incorporated , INGLE, Ajay Anant , CODRESCU, Lucian , VENKUMAHANTI, Suresh
发明人： INGLE, Ajay Anant , CODRESCU, Lucian , VENKUMAHANTI, Suresh
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3867
摘要： A device is disclosed that includes an instruction execution pipeline having multiple stages for executing an instruction. The device also includes a control logic circuit coupled to the instruction execution pipeline. The control logic circuit is adapted to skip at least one stage of the instruction execution pipeline during execution of the instruction. The control logic circuit is also adapted to execute at least one non-skipped stage during execution of the decoded instruction.
摘要翻译：公开了一种包括具有用于执行指令的多个级的指令执行流水线的装置。该装置还包括耦合到指令执行管线的控制逻辑电路。控制逻辑电路适于在执行指令期间跳过指令执行流水线的至少一个级。控制逻辑电路还适于在执行解码的指令期间执行至少一个非跳过级。

6. 发明申请

WO2014062445A1 SELECTIVE COUPLING OF AN ADDRESS LINE TO AN ELEMENT BANK OF A VECTOR REGISTER FILE 审中-公开
标题翻译：地址线的选择性耦合到矢量寄存器文件的元素银行
公开(公告)号：WO2014062445A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/064063
申请日：2013-10-09
申请人： QUALCOMM INCORPORATED
发明人： INGLE, Ajay Anant , HOFFMAN, Marc M. , MATHEW, Deepak
IPC分类号： G06F9/30
CPC分类号： G06F9/30141 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3012
摘要： A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.
摘要翻译：一种方法包括根据选择模式将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。该方法还包括通过单个读取端口访问由第一地址线选择性寻址的存储在第一元素库内的数据。

7. 发明申请

WO2013169836A1 PER THREAD CACHELINE ALLOCATION MECHANISM IN SHARED PARTITIONED CACHES IN MULTI-THREADED PROCESSORS 审中-公开
标题翻译：多线程处理器中共享分区缓存中的每个螺纹加速器分配机制
公开(公告)号：WO2013169836A1
公开(公告)日：2013-11-14
申请号：PCT/US2013/040040
申请日：2013-05-08
申请人： QUALCOMM INCORPORATED
发明人： KOOB, Christpher Edward , INGLE, Ajay Anant , CODRESCU, Lucian , VENKUMAHANTI, Suresh K.
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/0848 , G06F12/0864
摘要： Systems and methods for allocation of cache lines in a shared partitioned cache (104) of a multi-threaded processor (102). A memory management unit (110) is configured to determine attributes associated with an address for a cache entry associated with a processing thread (T0) to be allocated in the cache. A configuration register (CP 300_0) is configured to store cache allocation information based on the determined attributes. A partitioning register (DP 310) is configured to store partitioning information for partitioning the cache into two or more portions (Main/Aux in FIG. 3). The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.
摘要翻译：用于在多线程处理器（102）的共享分区高速缓存（104）中分配高速缓存行的系统和方法。存储器管理单元（110）被配置为确定与要在高速缓存中分配的处理线程（T0）相关联的高速缓存条目的地址相关联的属性。配置寄存器（CP 300_0）被配置为基于所确定的属性来存储高速缓存分配信息。分区寄存器（DP 310）被配置为存储用于将高速缓存分割成两个或更多个部分（图3中的主/辅助）的分区信息。基于配置寄存器和分区寄存器，缓存条目被分配到高速缓存的一部分中。

8. 发明申请

WO2011109476A1 SYSTEM AND METHOD OF PROCESSING HIERARCHICAL VERY LONG INSTRUCTION PACKETS 审中-公开
标题翻译：处理分层非常长的指令包的系统和方法
公开(公告)号：WO2011109476A1
公开(公告)日：2011-09-09
申请号：PCT/US2011/026815
申请日：2011-03-02
申请人： QUALCOMM INCORPORATED , CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant , VENKUMAHANTI, Suresh K. , TABONY, Charles Joseph
发明人： CODRESCU, Lucian , PLONDKE, Erich James , INGLE, Ajay Anant , VENKUMAHANTI, Suresh K. , TABONY, Charles Joseph
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3853 , G06F9/30149
摘要： A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.
摘要翻译：公开了一种处理分级非常长的指令字（VLIW）分组的系统和方法。在特定实施例中，公开了一种处理指令的方法。该方法包括：接收分层VLIW指令分组，并对来自分组的指令进行解码，以确定该指令是单个指令还是指令是否包括包含多个子指令的子分组。响应于确定指令包括子分组，该方法还包括执行每个子指令。

9. 发明申请

WO2007056675A3 ARITHMETHIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR 审中-公开
公开(公告)号：WO2007056675A3
公开(公告)日：2007-05-18
申请号：PCT/US2006/060500
申请日：2006-11-02
申请人： QUALCOMM INCORPORATED , AHMED, Muhammad , INGLE, Ajay Anant , JAMIL, Sujat
发明人： AHMED, Muhammad , INGLE, Ajay Anant , JAMIL, Sujat
IPC分类号： G06F9/355
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.

10. 发明申请

WO2014150733A1 DEVICE AND METHOD FOR COMPUTING A CHANNEL ESTIMATE 审中-公开
标题翻译：用于计算通道估计的装置和方法
公开(公告)号：WO2014150733A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/024089
申请日：2014-03-12
申请人： QUALCOMM INCORPORATED
发明人： MATHEW, Deepak , INGLE, Ajay Anant , ZENG, Mao , HOFFMAN, Marc M.
IPC分类号： H04B1/7093 , H04B1/7075 , H03H17/02
CPC分类号： H04L25/0212 , H04B1/70752 , H04B1/7093 , H04B2201/70707
摘要： An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.
摘要翻译：一种装置包括选择逻辑，其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。第一子集包括存储在第一组寄存器的第一寄存器中的第一样本，并且还包括存储在第一组寄存器的第二寄存器上的第二样本。该装置还包括移位逻辑，配置成移位存储在第二组寄存器中的第二组采样。该装置还包括信道估计器，其被配置为基于第一子集生成与信道估计相关联的第一值，并且还基于所移位的第二组样本的第二子集。

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