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    • 1. 发明申请
    • CLOCK SYNCHRONIZATION
    • 时钟同步
    • WO2018057262A1
    • 2018-03-29
    • PCT/US2017/049595
    • 2017-08-31
    • QUALCOMM INCORPORATED
    • BLACK, JustinWANG, Cheng-HanYANG, Jeongsik
    • H03L7/14H04W52/02
    • An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.
    • 公开了一种用于同步分布在无线设备内的时钟信号的装置和方法。 在一些实施例中,本地振荡器(LO)时钟信号被缓冲并分配给无线设备内的两个或更多个收发机。 每个收发器可以包括可配置的时钟分频器以分配分布式LO时钟信号并生成输出时钟信号。 相位检测器比较来自每个可配置时钟分频器的输出时钟信号,并根据确定的相位差生成输出信号。 相位检测器输出信号可以使可配置时钟分频器中的至少一个修改其相应的输出时钟信号,从而使不同的可配置时钟分频器之间的输出时钟信号同步。 在一些实施例中,来自可配置时钟分频器的时钟信号可被修改(移位)大约90或180度。
    • 7. 发明公开
    • SIMULTANEOUS EDGE TOGGLING IMMUNITY CIRCUIT FOR MULTI-MODE BUS
    • 用于多模总线的同步切换抗扰性电路
    • EP3213474A1
    • 2017-09-06
    • EP15794418.2
    • 2015-10-29
    • QUALCOMM INCORPORATED
    • PITIGOI-ARON, RaduBLACK, Justin
    • H04L25/49G06F13/42
    • G06F13/4291G06F13/364G06F13/4282H04L25/4923
    • A device is provided comprising a shared bus including a first and a second line, a first subset of devices and a second subset of devices coupled to the shared bus. The first subset of devices may be configured to operate according to a first protocol mode. The second subset of devices may be configured to operate according to a second protocol mode, wherein the second protocol mode is distinct from the first protocol mode. A first device within the first subset of devices may include a receiver circuit adapted to adjust a signal transition occurring on the first line while the second line is in a first logical state so that the signal transition instead occurs when the second line is in a second logical state. The signal transition is adjusted only if it occurs within a threshold amount of time from a second transition on the second line.
    • 提供包括共享总线的设备,所述共享总线包括第一和第二线路,第一设备子集以及耦合到所述共享总线的第二设备子集。 第一设备子集可以被配置为根据第一协议模式进行操作。 第二设备子集可以被配置为根据第二协议模式进行操作,其中第二协议模式不同于第一协议模式。 第一设备子集内的第一设备可以包括接收器电路,该接收器电路适于在第二线路处于第一逻辑状态时调整在第一线路上发生的信号转变,使得当第二线路处于第二状态 逻辑状态。 仅当信号转变发生在从第二条线上的第二转变开始的阈值时间量内时才调整信号转变。
    • 10. 发明申请
    • APPARATUS AND METHODS FOR SYNCHRONIZING A CONTROLLER AND SENSORS
    • 用于同步控制器和传感器的设备和方法
    • WO2017070593A2
    • 2017-04-27
    • PCT/US2016/058289
    • 2016-10-21
    • QUALCOMM INCORPORATED
    • PITIGOI-ARON, RaduSHEYNBLAT, LeonidPUIG, CarlosBLACK, JustinKULKARNI, Rashmi
    • G06F1/12
    • H04J3/0685G06F1/12G08C2201/20H04Q9/00
    • Disclosed are methods and apparatus for synchronizing a controller and sensors in a system. A timestamp is provided in a host controller of an interface event on an interface coupled with host controller through detecting a message from a sensor on the interface that identifies the issuance of the interface event caused by the sensor at a first time. In response, the controller issues first and second events on the interface at respective second and third times, while concurrently counting cycles of a clock in the controller after each issuance. The controller also receives a first and second sensor counts representing the internal sensor clock times noted for the first and second events. The controller may then accurately calculate the timestamp of the interface event corresponding to the first time based on both internal controller counts and the sensor counts without needing a timestamp from the sensor directly.
    • 公开了用于同步系统中的控制器和传感器的方法和设备。 在与主控制器耦合的接口上的接口事件的主控制器中通过检测来自接口上的传感器的消息来提供时间戳,所述消息识别第一时间由传感器引起的接口事件的发布。 作为响应,控制器分别在第二次和第三次在接口上发布第一和第二事件,同时在每次发布之后对控制器中的时钟周期进行计数。 该控制器还接收第一和第二传感器计数,该第一和第二传感器计数表示针对第一和第二事件记录的内部传感器时钟时间。 然后,控制器可以基于内部控制器计数和传感器计数精确地计算与第一次对应的接口事件的时​​间戳,而不需要直接来自传感器的时间戳。