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    • 3. 发明专利
    • Jtag power collapse debug
    • JTAG电源调试
    • JP2013047964A
    • 2013-03-07
    • JP2012223429
    • 2012-10-05
    • Qualcomm Incクゥアルコム・インコーポレイテッドQualcomm Incorporated
    • MATTHEW LEVI SEVERSONBURKE JOSEPH PATRICKPHILIP POTTIER
    • G06F11/28
    • G06F11/3656
    • PROBLEM TO BE SOLVED: To execute a debug operation on a processor after a power collapse.SOLUTION: Status registers of a processor are scanned by using a debugger. When a clock edge of a reference clock fails to appear on the pin of a re-synchronized timing clock RTCK of a JTAG interface in a certain period, a timeout condition is detected. The debugger enters a debug logical reset state. The debugger detects a next RTCK edge indicating that the processor has become active again. The debugger scans the status registers, and determines the current state of the processor. When the debugger determining that the processor was halted due to a power collapse, the debugger restores debug registers, ETM registers, ETB registers, or their arbitrary combination typically within 4 milliseconds. The debugger restarts the processor once the registers are restored.
    • 要解决的问题:在电源崩溃后对处理器执行调试操作。 解决方案:使用调试器扫描处理器的状态寄存器。 当某个时间段内的参考时钟的时钟沿不能出现在JTAG接口的同步定时时钟RTCK的引脚上时,检测到超时状态。 调试器进入调试逻辑复位状态。 调试器检测下一个RTCK边沿,指示处理器已经再次变为活动状态。 调试器扫描状态寄存器,并确定处理器的当前状态。 当调试器确定处理器由于电源崩溃而停止时,调试器通常在4毫秒内恢复调试寄存器,ETM寄存器,ETB寄存器或其任意组合。 调试器在恢复寄存器后重新启动处理器。 版权所有(C)2013,JPO&INPIT
    • 4. 发明专利
    • Combined digital-to-analog converter and signal filter
    • 组合数字到模拟转换器和信号滤波器
    • JP2013085256A
    • 2013-05-09
    • JP2012243911
    • 2012-11-05
    • Qualcomm Incクゥアルコム・インコーポレイテッドQualcomm Incorporated
    • BURKE JOSEPH PATRICK
    • H03M1/66H03M1/06H03M3/00H04B1/69
    • H03M1/0626H03M1/66H03M3/504H04B1/71635
    • PROBLEM TO BE SOLVED: To provide an analog low-pass filter which may be used in a variety of applications and in ultrawide band applications.SOLUTION: An electronic circuit for processing a digital signal 201 includes a plurality of digital delay circuits 203, 205, 207, each configured to produce a delayed replica of the digital signal; a plurality of digital-to-analog converters 211, 213, 215, 217, each configured to convert the digital signal or the delayed replica from one of the delay circuits into an analog signal; a plurality of analog gain circuits 221, 223, 225, 227, each configured to adjust the analog signal from the digital-to-analog converters by a gain factor and each having an output; and an analog summer 231 configured to sum the outputs of the analog gain circuits.
    • 要解决的问题:提供可用于各种应用和超宽带应用中的模拟低通滤波器。 解决方案:用于处理数字信号201的电子电路包括多个数字延迟电路203,205,207,每个数字延迟电路被配置为产生数字信号的延迟复制品; 多个数模转换器211,213,215,217,每个被配置为将数字信号或延迟的副本从一个延迟电路转换为模拟信号; 多个模拟增益电路221,223,225,227,其被配置为通过增益因子调整来自数模转换器的模拟信号,并且每个具有输出; 以及被配置为对模拟增益电路的输出求和的模拟加法器231。 版权所有(C)2013,JPO&INPIT