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1. 发明申请

US20080087958A1 SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR 审中-公开
标题翻译：带有DOPED晶体管的半导体器件
公开(公告)号：US20080087958A1
公开(公告)日：2008-04-17
申请号：US11951833
申请日：2007-12-06
申请人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
发明人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
IPC分类号： H01L27/088
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823857 , H01L27/11 , H01L29/66545 , H01L29/7833
摘要： A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.
摘要翻译：半导体器件提供具有第一区域和第二区域的衬底。牺牲第一栅极形成在第一区域中。源极/漏极形成在第一区域中。第二区域栅极电介质形成在第二区域中。第二区域栅极形成在第二区域栅极电介质上。在第二区域中形成第二区域源极/漏极。在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。牺牲的第一个门被暴露。通过去除牺牲第一栅极形成栅极空间。在栅极空间中形成第一区域栅极电介质。第一区栅极形成在第一区栅极电介质上。牺牲层被去除。

2. 发明申请

US20060252188A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD 有权
标题翻译：半导体器件和制造方法
公开(公告)号：US20060252188A1
公开(公告)日：2006-11-09
申请号：US10908328
申请日：2005-05-06
申请人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
发明人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823857 , H01L27/11 , H01L29/66545 , H01L29/7833
摘要： A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.
摘要翻译：用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。牺牲第一栅极形成在第一区域中。源极/漏极形成在第一区域中。第二区域栅极电介质形成在第二区域中。第二区域栅极形成在第二区域栅极电介质上。在第二区域中形成第二区域源极/漏极。在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。牺牲的第一个门被暴露。通过去除牺牲第一栅极形成栅极空间。在栅极空间中形成第一区域栅极电介质。第一区栅极形成在第一区栅极电介质上。牺牲层被去除。

3. 发明授权

US07326609B2 Semiconductor device and fabrication method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07326609B2
公开(公告)日：2008-02-05
申请号：US10908328
申请日：2005-05-06
申请人： Purakh Raj Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
发明人： Purakh Raj Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823857 , H01L27/11 , H01L29/66545 , H01L29/7833
摘要： A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.
摘要翻译：用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。牺牲第一栅极形成在第一区域中。源极/漏极形成在第一区域中。第二区域栅极电介质形成在第二区域中。第二区域栅极形成在第二区域栅极电介质上。在第二区域中形成第二区域源极/漏极。在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。牺牲的第一个门被暴露。通过去除牺牲第一栅极形成栅极空间。在栅极空间中形成第一区域栅极电介质。第一区栅极形成在第一区栅极电介质上。牺牲层被去除。

4. 发明申请

US20070090484A1 INTEGRATED CIRCUIT STRESS CONTROL SYSTEM 审中-公开
标题翻译：集成电路应力控制系统
公开(公告)号：US20070090484A1
公开(公告)日：2007-04-26
申请号：US11162027
申请日：2005-08-25
申请人： Jae Gon Lee , Cher Sian Chua , Chew Hoe Ang , Liang-Choo Hsia
发明人： Jae Gon Lee , Cher Sian Chua , Chew Hoe Ang , Liang-Choo Hsia
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7842
摘要： An integrated circuit stress control system is provided. A gate is formed on a substrate and a channel is formed in the substrate. A source/drain is formed around the gate. A shallow trench isolation is formed in the substrate, the shallow trench isolation producing strain on the channel. A stress suppressing feature is formed in the substrate.
摘要翻译：提供集成电路应力控制系统。栅极形成在衬底上，并且沟道形成在衬底中。源极/漏极围绕栅极形成。在衬底中形成浅沟槽隔离，通道上的浅沟槽隔离产生应变。在基板上形成应力抑制特征。

5. 发明申请

US20090146262A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECHNOLOGY 有权
标题翻译：采用选择性外延生长技术的集成电路系统
公开(公告)号：US20090146262A1
公开(公告)日：2009-06-11
申请号：US11952947
申请日：2007-12-07
申请人： Huang Liu , Alex K.H. See , James Lee , Johnny Widodo , Chung Woh Lai , Wenzhi Gao , Zhao Lun , Shailendra Mishra , Liang-Choo Hsia
发明人： Huang Liu , Alex K.H. See , James Lee , Johnny Widodo , Chung Woh Lai , Wenzhi Gao , Zhao Lun , Shailendra Mishra , Liang-Choo Hsia
IPC分类号： H01L29/04
CPC分类号： H01L21/02639 , H01L21/0237 , H01L21/02433 , H01L21/02521 , H01L21/02609 , H01L21/02636 , H01L21/76229 , H01L21/823807
摘要： An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.
摘要翻译：一种集成电路系统，包括：提供衬底; 在基板上沉积电介质; 在电介质上沉积隔离电介质; 通过隔离电介质和电介质形成沟槽以露出衬底; 在所述集成电路系统上沉积电介质衬垫; 处理介电衬垫以形成沟槽间隔物; 以及在所述沟槽内沉积外延生长，其包括基本上与所述衬底相同的晶体取向。

6. 发明授权

US07795680B2 Integrated circuit system employing selective epitaxial growth technology 有权
标题翻译：采用选择性外延生长技术的集成电路系统
公开(公告)号：US07795680B2
公开(公告)日：2010-09-14
申请号：US11952947
申请日：2007-12-07
申请人： Huang Liu , Alex K. H. See , James Lee , Johnny Widodo , Chung Woh Lai , Wenzhi Gao , Zhao Lun , Shailendra Mishra , Liang-Choo Hsia
发明人： Huang Liu , Alex K. H. See , James Lee , Johnny Widodo , Chung Woh Lai , Wenzhi Gao , Zhao Lun , Shailendra Mishra , Liang-Choo Hsia
IPC分类号： H01L29/04
CPC分类号： H01L21/02639 , H01L21/0237 , H01L21/02433 , H01L21/02521 , H01L21/02609 , H01L21/02636 , H01L21/76229 , H01L21/823807
摘要： An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.
摘要翻译：一种集成电路系统，包括：提供衬底; 在基板上沉积电介质; 在电介质上沉积隔离电介质; 通过隔离电介质和电介质形成沟槽以露出衬底; 在所述集成电路系统上沉积电介质衬垫; 处理介电衬垫以形成沟槽间隔物; 以及在所述沟槽内沉积外延生长，其包括基本上与所述衬底相同的晶体取向。

7. 发明申请

US20100009527A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR WELL FORMATION 审中-公开
标题翻译：集成电路系统采用单层掩模技术，形成良好的形成
公开(公告)号：US20100009527A1
公开(公告)日：2010-01-14
申请号：US12172724
申请日：2008-07-14
申请人： Yong Meng Lee , Chung Woh Lai , Huang Liu , Wenzhi Gao , Zhao Lun , Johnny Widodo , Shailendra Mishra , Liang-Choo Hsia
发明人： Yong Meng Lee , Chung Woh Lai , Huang Liu , Wenzhi Gao , Zhao Lun , Johnny Widodo , Shailendra Mishra , Liang-Choo Hsia
IPC分类号： H01L21/266
CPC分类号： H01L21/2652 , H01L21/26513 , H01L21/26586 , H01L21/823878 , H01L21/823892
摘要： A method for manufacturing an integrated circuit system that includes: providing a substrate; forming a mask layer over the substrate; implanting a first well through an opening in the mask layer into the substrate; and implanting a second well through the mask layer and the opening via a single implant into the substrate.
摘要翻译：一种集成电路系统的制造方法，包括：提供基板; 在衬底上形成掩模层; 将第一阱通过掩模层中的开口植入衬底中; 以及将第二阱通过所述掩模层和所述开口经由单个植入物注入到所述衬底中。

8. 发明申请

US20110316166A1 INTEGRATED CIRCUIT SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：集成电路系统及其制造方法
公开(公告)号：US20110316166A1
公开(公告)日：2011-12-29
申请号：US12825266
申请日：2010-06-28
申请人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
发明人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/7684
摘要： A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer.
摘要翻译：集成电路系统的制造方法包括：在体基板上形成蚀刻停止层; 在所述蚀刻停止层上形成缓冲层; 在缓冲层上形成硬掩模; 通过所述蚀刻停止层形成穿透硅通孔，所述硬掩模被检测并且所述缓冲层以低的下压力去除; 以及在穿通硅通孔和蚀刻停止层上形成钝化层。

9. 发明授权

US07445874B2 Method to resolve line end distortion for alternating phase shift mask 有权
标题翻译：解决交变相移掩模线路失真的方法
公开(公告)号：US07445874B2
公开(公告)日：2008-11-04
申请号：US10985263
申请日：2004-11-10
申请人： Sia Kim Tan , Qunying Lin , Liang-Choo Hsia
发明人： Sia Kim Tan , Qunying Lin , Liang-Choo Hsia
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G03F1/30
摘要： A embodiment method for forming a layout for a phase shift mask. A embodiment comprises providing a layout comprising a first feature, a first shifter region and a second shifter region. The first feature preferably has a L-shape portion with an elbow region. The first shifter region is on the outside of the L-shaped portion and the second shifter region is on the inside of the L-shaped portion. The elbow region has an outside corner away from the second shifter region. We identify a phase conflict region caused by the L-shaped portion of the first feature, the first shifter region and the second shifter region. We resolve the phase conflict by modifying the elbow region by moving the outside corner of the elbow region away from the first shifter region and the phase conflict region. The modification of the elbow region further comprises forming a jog region in the line end section of the first feature.
摘要翻译：一种用于形成相移掩模布局的实施例方法。实施例包括提供包括第一特征，第一移位区和第二移位区的布局。第一特征优选具有肘部区域的L形部分。第一移位区域位于L形部分的外侧，第二移位区域位于L形部分的内侧。肘部区域具有远离第二移位区域的外角。我们识别由第一特征的L形部分，第一移位区域和第二移位区域引起的相位冲突区域。我们通过移动肘部区域的外角远离第一移位区域和相位冲突区域来修改肘部区域来解决相位冲突。肘部区域的修改还包括在第一特征的线端部中形成点动区域。

10. 发明授权

US6048762A Method of fabricating embedded dynamic random access memory 失效
标题翻译：嵌入式动态随机存取存储器的制作方法
公开(公告)号：US6048762A
公开(公告)日：2000-04-11
申请号：US55577
申请日：1998-04-06
申请人： Liang-Choo Hsia , H. J. Wu
发明人： Liang-Choo Hsia , H. J. Wu
IPC分类号： H01L21/285 , H01L21/8242 , H01L27/108 , H01L21/8244
CPC分类号： H01L27/10852 , H01L21/28512 , H01L27/10808
摘要： A method of fabricating an embedded dynamic random access memory. Using the method of dual damascence, by forming patterning only one dielectric layer, the contact windows with different depth are formed. In addition, the metal layer formed within the metal connecting regions are used as interconnects without further process.
摘要翻译：一种制造嵌入式动态随机存取存储器的方法。使用双重阻力的方法，通过仅形成图案化的一个电介质层，形成具有不同深度的接触窗口。此外，形成在金属连接区域内的金属层用作互连而不进一步处理。

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