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    • 3. 发明授权
    • Interrupt-based hardware support for profiling memory system performance
    • 基于中断的硬件支持,用于分析内存系统性能
    • US5768500A
    • 1998-06-16
    • US749043
    • 1996-11-14
    • Prathima AgrawalAaron Jay GoldbergJohn Andrew Trotter
    • Prathima AgrawalAaron Jay GoldbergJohn Andrew Trotter
    • G06F9/48G06F11/34
    • G06F11/348G06F11/3409G06F11/3447G06F2201/805G06F2201/86G06F2201/88G06F2201/885
    • Fueled by higher clock rates and superscalar technologies, growth in processor speed continues to outpace improvement in memory system performance. Reflecting this trend, architects are developing increasingly complex memory hierarchies to mask the speed gap, compiler writers are adding locality enhancing transformations to better utilize complex memory hierarchies, and applications programmers are re-coding their algorithms to exploit memory systems. All of these groups need empirical data on memory behavior to guide their optimizations. This paper describes how to combine simple hardware support and sampling techniques to obtain such data without appreciably perturbing system performance. By augmenting a cache miss counter with a compare register and interrupt line such that the processor is interrupted when the counter matches the compare value, we can sample system state and develop cache miss profiles that associate cache misses with specific processes, procedures, call stacks, addresses, or user defined aspects of system state. This idea is implemented in the Mprof prototype that profiles data stall cycles, first level cache misses, and second level misses on the sun Sparc 10/41. Simple case studies are provided to illustrate Mprof's features.
    • 在更高的时钟频率和超标量技术的推动下,处理器速度的增长继续超过内存系统性能的提升。 反映这种趋势,架构师正在开发越来越复杂的内存层次来掩盖速度差距,编译器编写者正在增加局部性增强转换,以更好地利用复杂的内存层次,应用程序员正在重新编码其算法以利用内存系统。 所有这些组都需要关于记忆行为的实证数据来指导其优化。 本文介绍了如何组合简单的硬件支持和采样技术来获得这样的数据,而不会明显地扰乱系统性能。 通过增加具有比较寄存器和中断线的高速缓存未命中计数器,使得当计数器与比较值匹配时,处理器中断,我们可以对系统状态进行采样,并开发将高速缓存未命中与特定进程,过程,调用堆栈, 地址或用户定义的方面的系统状态。 这个想法是在Mprof原型中实现的,该原型在太阳Sparc 10/41上配置数据失速循环,一级高速缓存未命中和二级缺失。 提供简单的案例研究来说明Mprof的功能。
    • 5. 发明授权
    • Priority access for real-time traffic in contention-based networks
    • 在基于争用的网络中实时流量的优先级访问
    • US06611529B1
    • 2003-08-26
    • US09261693
    • 1999-03-03
    • Anjur Sundaresan KrishnakumarJoao Luis SobrinhoJohn Andrew Trotter
    • Anjur Sundaresan KrishnakumarJoao Luis SobrinhoJohn Andrew Trotter
    • H04J316
    • H04L12/40163H04L12/413H04L12/44
    • In a contention-based network, a station, whose transmission is colliding with the transmission of another station and which heretofore would have transmitted a data packet immediately following its colliding transmission—as, for example, in a blackburst contention—suspends transmission immediately upon termination of the collision and, if necessary, at a particular point(s) in time during the collision. The station recommences transmission after a predetermined non-zero duration of time, or “time notch”, during which the medium is idle. In particular, a station that has won a blackburst contention separates its blackburst signal from its subsequent data transmission by a certain amount of time during which the medium is idle. Moreover, a station participating in a blackburst contention may cause the occurrence of a time notch at particular points in time during the contention in order that its access priority vis-a-vis other stations be determined.
    • 在基于争用的网络中,其传输正在与另一站的传输相冲突,并且其将在其冲突传输之后立即传输数据分组,例如在黑爆争用中立即在终止时暂停传输 的碰撞,如有必要,在碰撞期间的特定时间点。 在该介质空闲之后,该站重新开始经过预定的非零持续时间或“时间缺口”之后的传输。 特别地,已经赢得黑爆争端的站将其黑爆信号与其后续数据传输分离一定量的介质空闲时间。 此外,参与黑名单争用的电台可能会在争用期间的特定时间点发生时差,以便确定其对其他电台的访问优先级。
    • 6. 发明授权
    • Variable bitrate radio modem system to enhance data transmission and
reduce error rates
    • 可变比特率无线调制解调器系统,以增强数据传输并降低错误率
    • US5862141A
    • 1999-01-19
    • US665131
    • 1996-06-14
    • John Andrew Trotter
    • John Andrew Trotter
    • H04L1/00H04J3/22
    • H04L1/0002H04L1/0025
    • Disclosed is a variable bitrate radio modem unit that includes a transmit section and a receive section that are linked through a host computer. In the transmit section, the host computer is connected to a data modulator equipped with a variable bitrate data generator which in turn is connected to a radio transmit modem. In the receive section, a radio receive modem is connected to a clock/data recovery circuit which in turn is connected to an error detection and correction circuit. The error detection and correction circuit is then connected to the host computer. A connection is established at a predetermined bitrate between two host computers of two individual radio modem units. While data is being transmitted back and forth, the error rate of the data being received is determined by the error detection circuit. If the error rate is larger than a predetermined rate, the bitrate of the radio transmit modem of the transmitting unit is reduced. Conversely, if the error rate is smaller than a second predetermined rate, the bitrate of the radio transmit modem of the transmitting unit is increased.
    • 公开了一种可变比特率无线电调制解调器单元,其包括通过主计算机链接的发送部分和接收部分。 在发送部分中,主计算机连接到配备有可变比特率数据发生器的数据调制器,该可变比特率数据发生器又连接到无线电发射调制解调器。 在接收部分中,无线电接收调制解调器连接到时钟/数据恢复电路,时钟/数据恢复电路又连接到错误检测和校正电路。 然后将错误检测和校正电路连接到主机。 在两个单独的无线电调制解调器单元的两个主计算机之间以预定比特率建立连接。 当数据来回传输时,接收到的数据的错误率由误差检测电路确定。 如果错误率大于预定速率,则减少发送单元的无线电发送调制解调器的比特率。 相反,如果错误率小于第二预定速率,则发送单元的无线电发送调制解调器的比特率增加。