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1. 发明授权

US06518070B1 Process of forming a semiconductor device and a semiconductor device 失效
标题翻译：形成半导体器件和半导体器件的工艺
公开(公告)号：US06518070B1
公开(公告)日：2003-02-11
申请号：US09571586
申请日：2000-05-17
申请人： Prasad V. Alluri , Mark Victor Raymond , Sucharita Madhukar , Roland R. Stumpf , Chun-Li Liu , Clarence J. Tracy
发明人： Prasad V. Alluri , Mark Victor Raymond , Sucharita Madhukar , Roland R. Stumpf , Chun-Li Liu , Clarence J. Tracy
IPC分类号： H01L2170
CPC分类号： H01L21/3212 , H01L27/1057 , H01L27/108 , H01L27/10844 , H01L27/10852 , H01L27/10882 , H01L28/55 , H01L28/60 , H01L28/65
摘要： A process for forming a capacitor with a high-k dielectric or ferroelectric layer within a semiconductor device is used to reduce the likelihood of oxidation or materials interactions between that layer and an underlying layer. A first electrode layer includes atoms that form along grain boundaries within the first electrode layer to reduce the oxidation of a conductive plug or undesired materials interactions.
摘要翻译：用于在半导体器件内形成具有高k电介质层或铁电体层的电容器的工艺被用于降低该层与下层之间的氧化或材料相互作用的可能性。第一电极层包括沿第一电极层内的晶界形成的原子，以减少导电塞的氧化或不期望的材料相互作用。

2. 发明授权

US07932189B2 Process of forming an electronic device including a layer of discontinuous storage elements 有权
标题翻译：形成包括不连续存储元件层的电子器件的工艺
公开(公告)号：US07932189B2
公开(公告)日：2011-04-26
申请号：US11627817
申请日：2007-01-26
申请人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
发明人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
IPC分类号： H01L21/31
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/11524 , H01L29/7887 , Y10S977/932 , Y10S977/943
摘要： An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.
摘要翻译：电子设备可以包括不连续的存储元件层。覆盖不连续存储元件的电介质层可以是基本上无氢的。形成电子器件的工艺可以包括在不连续的存储元件上形成包括硅的层。在一个实施方案中，该方法包括至少基本上氧化所有该层。在另一个实施方案中，该方法包括使用基本上无氢的硅前体材料形成层并至少基本上全部氧化。

3. 发明授权

US07928502B2 Transistor devices with nano-crystal gate structures 有权
标题翻译：具有纳米晶体栅结构的晶体管器件
公开(公告)号：US07928502B2
公开(公告)日：2011-04-19
申请号：US12715947
申请日：2010-03-02
申请人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
发明人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
IPC分类号： H01L29/792 , H01L29/76
CPC分类号： H01L29/7883 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/66825 , H01L29/78
摘要： Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
摘要翻译：非易失性半导体器件的实施例包括其中具有源极区域和漏极区域的衬底，所述源极区域和漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。栅极结构包括基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层，以及叠加在一个以上杂质阻挡层上的栅极导体层。可以使用最靠近栅极导体的阻挡层来调节器件的阈值电压和/或从栅极导体层延迟掺杂剂的扩散。

4. 发明授权

US07700438B2 MOS device with nano-crystal gate structure 有权
标题翻译：具有纳米晶体栅结构的MOS器件
公开(公告)号：US07700438B2
公开(公告)日：2010-04-20
申请号：US11343624
申请日：2006-01-30
申请人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
发明人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7883 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/66825 , H01L29/78
摘要： Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
摘要翻译：为非易失性半导体器件提供了方法和装置。该装置包括其中具有源极区域和漏极区域的衬底，漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。栅极结构包括：基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层和覆盖一个以上杂质阻挡层的栅极导体层。最靠近栅极导体的阻挡层也可用于调节器件的阈值电压和/或从栅极导体层延迟掺杂剂扩散。

5. 发明授权

US07683443B2 MOS devices with multi-layer gate stack 有权
标题翻译：具有多层门极堆叠的MOS器件
公开(公告)号：US07683443B2
公开(公告)日：2010-03-23
申请号：US12347061
申请日：2008-12-31
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker
IPC分类号： H01L29/76
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.
摘要翻译：半导体器件的实施例包括半导体衬底，其具有主表面，间隔开的源极和漏极区域，其在主表面处由沟道区域分隔开，并且多层栅极结构位于沟道区域上方。多层栅极结构包括与沟道区接触的栅极电介质层，包括覆盖栅极电介质层的金属氧化物的第一导体，覆盖第一导体的第二导体以及在栅极介电层和第二导体之间的杂质迁移抑制层第一导体或第一导体与第二导体之间。

6. 发明申请

US20080182428A1 ELECTRONIC DEVICE INCLUDING A LAYER OF DISCONTINUOUS STORAGE ELEMENTS AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括不连续存储元件层的电子设备和形成电子设备的方法
公开(公告)号：US20080182428A1
公开(公告)日：2008-07-31
申请号：US11627817
申请日：2007-01-26
申请人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
发明人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
IPC分类号： H01L21/31
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/11524 , H01L29/7887 , Y10S977/932 , Y10S977/943
摘要： An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.
摘要翻译：电子设备可以包括不连续的存储元件层。覆盖不连续存储元件的电介质层可以是基本上无氢的。形成电子器件的过程可以包括在不连续的存储元件上形成包括硅的层。在一个实施方案中，该方法包括至少基本上氧化所有该层。在另一个实施方案中，该方法包括使用基本上无氢的硅前体材料形成该层并至少基本上全部氧化。

7. 发明授权

US07195963B2 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US07195963B2
公开(公告)日：2007-03-27
申请号：US10851347
申请日：2004-05-21
申请人： Marius K. Orlowski , Chun-Li Liu , Choh-Fei Yeap
发明人： Marius K. Orlowski , Chun-Li Liu , Choh-Fei Yeap
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/1033 , H01L29/66628 , H01L29/66742 , H01L29/66772 , H01L29/7834 , H01L29/78606 , H01L29/78639 , H01L29/78687
摘要： Silicon carbon is used as a diffusion barrier to germanium so that a silicon layer can be subsequently formed without being contaminated with germanium. This is useful in separating silicon layers from silicon germanium layers in situations in which both silicon and silicon germanium are desired to be present on the same semiconductor device such as for providing different materials for optimizing carrier mobility between N and P channel transistors and for a raised source/drain of silicon in the case of a silicon germanium body.
摘要翻译：硅碳被用作锗的扩散阻挡层，从而可以随后形成硅层而不被锗污染。这在硅硅层分离的同时，硅和硅锗希望存在于同一半导体器件上，例如为了提供不同的材料以优化N沟道晶体管和P沟道晶体管之间的载流子迁移率，在硅锗体的情况下硅的源极/漏极。

8. 发明申请

US20100155825A1 TRANSISTOR DEVICES WITH NANO-CRYSTAL GATE STRUCTURES 有权
标题翻译：具有纳米晶体结构的晶体管器件
公开(公告)号：US20100155825A1
公开(公告)日：2010-06-24
申请号：US12715947
申请日：2010-03-02
申请人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
发明人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
IPC分类号： H01L29/792
CPC分类号： H01L29/7883 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/66825 , H01L29/78
摘要： Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
摘要翻译：非易失性半导体器件的实施例包括其中具有源极区域和漏极区域的衬底，所述源极区域和漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。栅极结构包括基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层，以及叠加在一个以上杂质阻挡层上的栅极导体层。可以使用最靠近栅极导体的阻挡层来调节器件的阈值电压和/或从栅极导体层延迟掺杂剂的扩散。

9. 发明申请

US20100059860A1 COUNTER-DOPED VARACTOR STRUCTURE AND METHOD 有权
标题翻译：计数器变结构和方法
公开(公告)号：US20100059860A1
公开(公告)日：2010-03-11
申请号：US12207127
申请日：2008-09-09
申请人： Chun-Li Liu , Olin L. Hartin , Jay P. John , James A. Kirchgessner , Vishal P. Trivedi
发明人： Chun-Li Liu , Olin L. Hartin , Jay P. John , James A. Kirchgessner , Vishal P. Trivedi
IPC分类号： H01L21/329 , H01L29/93
CPC分类号： H01L29/66174 , H01L29/93
摘要： An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.
摘要翻译：通过提供一种具有第一表面（43）的衬底（41），其中在第一表面（43）附近形成有P +区域（53,46），第一N区域（54），45），位于所述P +区（53,46）下方的N阱区（56,44）和位于所述第一N区（54,45）之下的第一P反掺杂区（55）区域（54,45）和N阱区域（56,44），从而形成用于变容二极管的P + NPN结构。在一些实施例中，第二P型反掺杂区域（59）设置在N阱区域（56,44）内，以便减小N阱区域（56,44）内的N掺杂浓度，但是不产生其中一个PN结。净掺杂分布（52）提供具有比可变电抗器（20）更大的调谐比率的变容二极管（40），而不具有这样的反掺杂区域。通过交换N和P区域，获得N + PNP变容二极管。

10. 发明申请

US20070176247A1 MOS device with multi-layer gate stack 有权
标题翻译：具有多层栅极堆叠的MOS器件
公开(公告)号：US20070176247A1
公开(公告)日：2007-08-02
申请号：US11343623
申请日：2006-01-30
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker
IPC分类号： H01L29/94
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.
摘要翻译：为半导体器件提供了方法和装置。该装置包括其中具有源极区和漏极区的衬底，漏极区被延伸到衬底的第一表面的沟道区分离，以及位于沟道区上方的多层栅极结构。栅极结构包括：栅极电介质，优选地与沟道区基本上接触的Hf，Zr或HfZr的氧化物，例如覆盖栅极电介质的MoSi的氧化物的第一导体层，例如多晶硅，覆盖在第一导体层上并且适于向沟道区施加电场，以及位于第一导体层上方或下方的杂质迁移抑制层（例如MoSi），并适于抑制移动杂质，例如氧气，朝向衬底。

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