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1. 发明授权

US6163876A Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow 有权
标题翻译：用于验证在高级合成流程中由计划行为产生的RTL的方法
公开(公告)号：US6163876A
公开(公告)日：2000-12-19
申请号：US187927
申请日：1998-11-06
申请人： Pranav Ashar , Subhrajit Bhattacharya , Anand Raghunathan , Akira Mukaiyama
发明人： Pranav Ashar , Subhrajit Bhattacharya , Anand Raghunathan , Akira Mukaiyama
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A complete procedure for verifying register-transfer logic against its scheduled behavior in a high-level synthesis environment is provided. A new method that is both complete and practical for verification is provided. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high-level synthesis--performed manually or by means of high-level synthesis software--proceeds from the algorithmic description of the design to structural RTL through a sequence of very well defined steps, each limited in its scope. Equivalence checking task is partitioned into two simpler subtasks, verifying the validity of register sharing, and verifying correct synthesis of the RYL interconnect and control. While state space traversal is unavoidable for verifying validity of the register sharing, irrelevant portions of the design are automatically abstracted out, significantly simplifying the task that must be performed by a back-end model checker.
摘要翻译：提供了一种在高级合成环境中验证寄存器传输逻辑与其调度行为的完整过程。提供了一种完整和实用的验证方法。已知硬件验证是一个困难的问题，并且所提出的验证技术利用了手动或通过高级合成软件执行的高级合成 - 从设计的算法描述到结构化RTL的顺序非常明确的步骤，每个都限于其范围。等效检查任务分为两个简单的子任务，验证寄存器共享的有效性，验证RYL互连和控制的正确合成。虽然状态空间遍历对于验证寄存器共享的有效性是不可避免的，但是设计的不相关部分被自动抽出，从而显着简化了后端模型检查器必须执行的任务。

2. 发明授权

US06745160B1 Verification of scheduling in the presence of loops using uninterpreted symbolic simulation 失效
标题翻译：使用未解释的符号仿真验证在存在循环的情况下的调度
公开(公告)号：US06745160B1
公开(公告)日：2004-06-01
申请号：US09414815
申请日：1999-10-08
申请人： Pranav Ashar , Anand Raghunathan , Subhrajit Bhattacharya , Aarti Gupta
发明人： Pranav Ashar , Anand Raghunathan , Subhrajit Bhattacharya , Aarti Gupta
IPC分类号： G06F1750
CPC分类号： G06F17/504
摘要： A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine a sufficient set of acyclic threads when loops are present, performing symbolic simulation to extract the above loop invariants, and proving equivalence of the acyclic threads. Systems, computer systems and computer program products that incorporate the techniques of verification and correctness checking according to the present invention have also been disclosed.
摘要翻译：一种检查电路调度的正确性的方法，其中从行为描述获得电路的调度。该方法包括提取循环不变量以在存在循环时确定足够的非循环线程集合，执行符号仿真以提取上述循环不变量，以及证明非循环线程的等价性。还公开了结合根据本发明的验证和正确性检查技术的系统，计算机系统和计算机程序产品。

3. 发明授权

US07383166B2 Verification of scheduling in the presence of loops using uninterpreted symbolic simulation 有权
标题翻译：使用未解释的符号仿真验证在存在循环的情况下的调度
公开(公告)号：US07383166B2
公开(公告)日：2008-06-03
申请号：US10756303
申请日：2004-01-14
申请人： Pranav Ashar , Anand Raghunathan , Subhrajit Bhattacharya
发明人： Pranav Ashar , Anand Raghunathan , Subhrajit Bhattacharya
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine a sufficient set of acyclic threads when loops are present, performing symbolic simulation to extract the above loop invariants, and proving equivalence of the acyclic threads. Systems, computer systems and computer program products that incorporate the techniques of verification and correctness checking according to the present invention have also been disclosed.
摘要翻译：一种检查电路调度的正确性的方法，其中从行为描述获得电路的调度。该方法包括提取循环不变量以在存在循环时确定足够的非循环线程集合，执行符号仿真以提取上述循环不变量，以及证明非循环线程的等价性。还公开了结合根据本发明的验证和正确性检查技术的系统，计算机系统和计算机程序产品。

4. 发明申请

US20070022395A1 POWER ESTIMATION EMPLOYING CYCLE-ACCURATE FUNCTIONAL DESCRIPTIONS 失效
标题翻译：功率估计使用周期精度功能描述
公开(公告)号：US20070022395A1
公开(公告)日：2007-01-25
申请号：US11278182
申请日：2006-03-31
申请人： Srivaths Ravi , Anand Raghunathan , Lin Zhong , Niraj Jha
发明人： Srivaths Ravi , Anand Raghunathan , Lin Zhong , Niraj Jha
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches.
摘要翻译：一种用于估计设计中的电子电路的功耗的方法，其采用循环精确功能描述（CAFD），其有利地提供通过RTL功率估计获得的精度，其具有高级方法的速度和速度。

5. 发明授权

US06625781B2 Multi-level power macromodeling 有权
公开(公告)号：US06625781B2
公开(公告)日：2003-09-23
申请号：US09771100
申请日：2001-01-26
申请人： Wolfgang Roethig , Ganesh Lakshminarayana , Anand Raghunathan , Arun Balakrishnan
发明人： Wolfgang Roethig , Ganesh Lakshminarayana , Anand Raghunathan , Arun Balakrishnan
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F2217/78
摘要： The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model. The present invention also models a power arc from one input pin to multiple output pins.

6. 发明申请

US20100088492A1 SYSTEMS AND METHODS FOR IMPLEMENTING BEST-EFFORT PARALLEL COMPUTING FRAMEWORKS 有权
标题翻译：实施最佳平衡计算框架的系统和方法
公开(公告)号：US20100088492A1
公开(公告)日：2010-04-08
申请号：US12399195
申请日：2009-03-06
申请人： Srimat Chakradhar , Anand Raghunathan , Jiayuan Meng
发明人： Srimat Chakradhar , Anand Raghunathan , Jiayuan Meng
IPC分类号： G06F9/30
CPC分类号： G06F9/545 , G06F8/00 , G06F9/4887 , G06F2209/485 , G06F2209/542
摘要： Implementations of the present principles include Best-effort computing systems and methods. In accordance with various exemplary aspects of the present principles, a application computation requests directed to a processing platform may be intercepted and classified as either guaranteed computations or best-effort computations. Best-effort computations may be dropped to improve processing performance while minimally affecting the end result of application computations. In addition, interdependencies between best-effort computations may be relaxed to improve parallelism and processing speed while maintaining accuracy of computation results.
摘要翻译：本原则的实施包括尽力而为的计算系统和方法。根据本原理的各种示例性方面，针对处理平台的应用计算请求可被截取并分类为保证计算或尽力而为计算。可以降低最大的努力以提高处理性能，同时最小程度上影响应用程序计算的最终结果。此外，可以放宽努力计算之间的相互依赖性，以提高并行性和处理速度，同时保持计算结果的准确性。

7. 发明授权

US07173906B2 Flexible crossbar switching fabric 失效
标题翻译：灵活的交叉开关织物
公开(公告)号：US07173906B2
公开(公告)日：2007-02-06
申请号：US10097582
申请日：2002-03-15
申请人： Srivaths Ravi , Anand Raghunathan , Jacob Chang
发明人： Srivaths Ravi , Anand Raghunathan , Jacob Chang
IPC分类号： H04J1/16 , H04Q11/00 , H04L12/56 , H04L12/54 , G06F13/00
CPC分类号： H04L49/101 , H04L45/24 , H04L49/205 , H04L49/254 , H04L49/3018
摘要： A crossbar switching fabric comprising a plurality of crossbar input ports and a plurality of crossbar output ports. The traffic from at least one source is directed to more than one of the plurality of crossbar input ports. The traffic from more than one crossbar output port is directed to at least one destination.
摘要翻译：一种交叉开关结构，包括多个交叉开关输入端口和多个交叉开关输出端口。来自至少一个源的业务被引导到多个交叉开关输入端口中的一个以上。来自多个横梁输出端口的流量被定向到至少一个目的地。

8. 发明申请

US20060058994A1 Power estimation through power emulation 审中-公开
标题翻译：通过电源仿真进行功率估计
公开(公告)号：US20060058994A1
公开(公告)日：2006-03-16
申请号：US11059839
申请日：2005-02-17
申请人： Srivaths Ravi , Anand Raghunathan , Joel Coburn
发明人： Srivaths Ravi , Anand Raghunathan , Joel Coburn
IPC分类号： G06F9/455
CPC分类号： G06F17/5022 , G06F2217/78
摘要： The time required to estimate the amount of power that will be consumed by a circuit under design is significantly speeded up. Specifically, the steps involved in power estimation (power model evaluation, aggregation) are implemented as power estimation circuitry that is added to the design of the functional circuit during circuit design. The resulting power-model-enhanced circuit is mapped onto a hardware emulation platform, one of whose outputs is a computation of the estimated power computed by the power estimation circuitry during the emulation. As compared to state-of-the-art commercial power estimation tools, speed-ups from around 10-fold to over 500-fold can be realized.
摘要翻译：估计设计中电路消耗的功率所需的时间显着加快。具体来说，功率估计（功率模型评估，聚合）中涉及的步骤被实现为在电路设计期间被添加到功能电路的设计的功率估计电路。所得到的功率模型增强电路被映射到硬件仿真平台上，其中一个输出是在仿真期间由功率估计电路计算的估计功率的计算。与最先进的商业功率估算工具相比，可以实现从10倍到超过500倍的加速。

9. 发明授权

US06978425B1 Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners 有权
标题翻译：使用通信架构调谐器设计用于片上系统的高性能通信架构的方法
公开(公告)号：US06978425B1
公开(公告)日：2005-12-20
申请号：US09576956
申请日：2000-05-24
申请人： Anand Raghunathan , Ganesh Lakshminarayana , Kanishka Lahiri , Sujit Dey
发明人： Anand Raghunathan , Ganesh Lakshminarayana , Kanishka Lahiri , Sujit Dey
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505
摘要： A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating communication analysis graph (CAG). Partitioning communication instances to create partition clusters. Evaluating cluster statistics related to the partition clusters and assigning parameter values to the partition clusters to form a new system with new communication architecture. Reanalyzing the new system and recomputing performance metrics. If performance is improved then synthesizing CATs to realize optimized protocols. If performance is not improved then the process is repeated.
摘要翻译：一种设计通信架构的方法，包括接收分区系统，通信架构拓扑，输入轨迹和性能矩阵。分析和创建通信分析图（CAG）。分区通信实例来创建分区集群。评估与分区集群相关的集群统计信息，并将参数值分配给分区集群，以形成具有新通信体系结构的新系统。重新分析新系统并重新计算性能指标。如果性能提高，那么合成CAT来实现优化协议。如果性能没有改善，则重复该过程。

10. 发明授权

US5726996A Process for dynamic composition and test cycles reduction 失效
标题翻译：动态组合和测试循环缩减的过程
公开(公告)号：US5726996A
公开(公告)日：1998-03-10
申请号：US529940
申请日：1995-09-18
申请人： Srimat T. Chakradhar , Anand Raghunathan
发明人： Srimat T. Chakradhar , Anand Raghunathan
IPC分类号： G01R31/28 , G01R31/3183 , G06F11/22
CPC分类号： G01R31/318392
摘要： A new dynamic process for test sequence compaction and test cycle reduction that identifies bottlenecks that prevent vector compaction and test cycle reduction for test sequences generated initially and generates subsequent test sequences with the aim of eliminating bottlenecks of the initially generated test sequences. To apply the process to sequential circuits, a sliding anchor frame technique is used that involves specifying the unspecified bits of a partially specified test sequence to detect other faults.
摘要翻译：测试序列压缩和测试周期缩减的新动态过程，其识别阻止最初生成的测试序列的向量压缩和测试周期减少的瓶颈，并生成后续测试序列，目的是消除初始生成的测试序列的瓶颈。为了将过程应用于顺序电路，使用滑动锚帧技术，其涉及指定部分指定的测试序列的未指定比特以检测其他故障。

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