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1. 发明专利

JP2009231637A Semiconductor-package structure for heat-dissipating piece 有权
标题翻译：散热片的半导体封装结构
公开(公告)号：JP2009231637A
公开(公告)日：2009-10-08
申请号：JP2008076808
申请日：2008-03-24
申请人： Powertech Technology Inc , 力成科技股▲ふん▼有限公司
发明人： YU BINGXUN , HONG JINWEI
IPC分类号： H01L23/12 , H01L23/29
CPC分类号： H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor-package structure having a heat-dissipating piece. SOLUTION: The semiconductor-package structure having the heat-dissipating pieces is constituted of a substrate, having a chip-carrier region and surrounding and forming a plurality of bored holes around the chip-carrier region and chips fitted in the chip-carrier region and electrically connected to the substrate. The semiconductor-package structure having the heat-dissipating pieces is, further, constituted of the heat-dissipating pieces suitable for the upper sections of the chips and having a plurality of supporting sections, extending from the upper surface to the lower surface of the substrate through boring, and package gel coating the chips and the partial substrate and the heat-dissipating pieces. Heat-dissipating effect is increased by the support sections for the heat-dissipating pieces, and warpage of package can be reduced. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有散热片的半导体封装结构。解决方案：具有散热片的半导体封装结构由具有芯片载体区域并围绕芯片载体区域周围并形成多个钻孔的基板和装配在芯片载体区域中的芯片构成，载体区域并且电连接到衬底。具有散热片的半导体封装结构还由适用于芯片的上部的散热片构成，并且具有从基板的上表面延伸到下表面的多个支撑部通过镗孔，并将芯片和部分基板以及散热片进行包胶。通过用于散热片的支撑部分增加散热效果，并且可以减小包装的翘曲。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009231296A Heat radiation type multiple hole semiconductor package 有权
标题翻译：热辐射型多孔半导体封装
公开(公告)号：JP2009231296A
公开(公告)日：2009-10-08
申请号：JP2008070841
申请日：2008-03-19
申请人： Powertech Technology Inc , 力成科技股▲分▼有限公司
发明人： YU BING-SHUN , HONG JINWEI
IPC分类号： H01L23/12
CPC分类号： H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a heat radiation type multiple hole semiconductor package for preventing a built-in heat sink from being separated by reinforcing heat radiation properties and reducing the warpage of a substrate. SOLUTION: The heat radiation type multiple hole semiconductor package includes: the substrate 210; a chip 220; the built-in type heat sink 230; and a sealed body 240. The substrate 210 includes: an upper surface 211, a lower surface 212, and a plurality of positioning holes 213; the chip 220 is installed on the upper surface 211; and the built-in type heat sink 230 is stuck to the chip 220. The built-in type heat sink 230 includes a plurality of support leads 231 and a heat radiation surface 232, and the group of support leads 231 is inserted into the group of positioning holes 213. Since the group of positioning holes 213 is not fully filled into the group of support leads 231, a plurality of mold flow passages 241 are formed. The sealed body 240 is formed on the upper surface 211 to seal the chip 220 and the built-in type heat sink 230. By exposing the heat radiation surface 232 and filling the mold flow passage 241, the group of support leads 231 is covered. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种散热型多孔半导体封装，用于通过加强散热性能和减少基板的翘曲来防止内置的散热器被分离。散热型多孔半导体封装包括：基板210; 芯片220; 内置式散热器230; 和密封体240.基板210包括：上表面211，下表面212和多个定位孔213; 芯片220安装在上表面211上; 并且内置型散热器230粘附到芯片220.内置型散热器230包括多个支撑引线231和散热表面232，并且该组支撑引线231插入到该组定位孔213的一组定位孔213未被完全填充到一组支撑引线231中，形成多个模流通道241。密封体240形成在上表面211上，以密封芯片220和内置型散热器230.通过暴露散热表面232并填充模具流动通道241，覆盖了一组支撑引线231。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009231295A Semiconductor device, and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009231295A
公开(公告)日：2009-10-08
申请号：JP2008070840
申请日：2008-03-19
申请人： Powertech Technology Inc , 力成科技股▲分▼有限公司
发明人： CHEN CHIN-TI , HONG JINWEI , YU BING-SHUN , WANG CHIN-FA
IPC分类号： H01L21/02 , H01L23/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a substrate identification code allowing quality control and an abnormality tracing without changing a using appearance.
SOLUTION: This semiconductor device is provided with a substrate 110, a chip 120 and the substrate identification code 130. The substrate 110 has an upper surface 111 and a lower surface 112, has a wiring layer 113 and a solder mask layer 114 formed on the lower surface 112 and further has a non-wiring region 115, and the solder mask layer 114 almost covers the wiring layer 113 and the non-wiring region 115. The chip 120 is installed on the upper surface 111 of the substrate 110, and the substrate identification code 130 is baked on the lower surface 112 of the substrate 110 by using a laser engraving method.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有允许质量控制和异常跟踪的基板识别码而不改变使用外观的半导体器件。解决方案：该半导体器件设置有衬底110，芯片120和衬底识别码130.衬底110具有上表面111和下表面112，具有布线层113和焊料掩模层114 形成在下表面112上并且还具有非布线区域115，并且焊料掩模层114几乎覆盖布线层113和非布线区域115.芯片120安装在基板110的上表面111上，并且通过使用激光雕刻方法在基板110的下表面112上烘烤基板识别代码130。版权所有（C）2010，JPO＆INPIT

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