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1. 发明申请

US20090278767A1 Data Access Method for a Timing Controller of a Flat Panel Display and Related Device 有权
标题翻译：平板显示器和相关设备的定时控制器的数据访问方法
公开(公告)号：US20090278767A1
公开(公告)日：2009-11-12
申请号：US12188221
申请日：2008-08-08
申请人： Po-Jui Huang , Ying-Jie Su , Chung-Jr Jan
发明人： Po-Jui Huang , Ying-Jie Su , Chung-Jr Jan
IPC分类号： G09G3/20
CPC分类号： G09G3/2092 , G09G3/3611 , G09G5/42
摘要： A data access method for a timing controller of a flat panel display includes forming a line buffer including a plurality of memory cells in the timing controller, dividing the plurality of memory cells into a first section and a second section, wherein the number of memory cells in the first section is greater than the number of memory cells in the second section, writing a first number of pixel data into the first section, wherein the first number of pixel data is included in a plurality of pixel data corresponding to a row of a frame, writing a second number of pixel data into the second section, wherein the second number of pixel data is included in the plurality of pixel data, and the first number is equal to the second number, and reading the plurality of pixel data from the plurality of memory cells according to an order.
摘要翻译：用于平板显示器的定时控制器的数据存取方法包括在定时控制器中形成包括多个存储单元的行缓冲器，将多个存储单元分成第一部分和第二部分，其中存储单元的数量在第一部分中大于第二部分中的存储器单元的数量，将第一数量的像素数据写入第一部分，其中第一数量的像素数据被包括在对应于一行的像素数据的多个像素数据中在所述第二部分中写入第二数量的像素数据，其中所述第二数量的像素数据被包括在所述多个像素数据中，并且所述第一数目等于所述第二数量，并且从所述第二数量读取所述多个像素数据多个存储单元。

2. 发明授权

US08274449B2 Data access method for a timing controller of a flat panel display and related device 有权
标题翻译：平板显示器及相关装置的定时控制器的数据存取方法
公开(公告)号：US08274449B2
公开(公告)日：2012-09-25
申请号：US12188221
申请日：2008-08-08
申请人： Po-Jui Huang , Ying-Jie Su , Chung-Jr Jan
发明人： Po-Jui Huang , Ying-Jie Su , Chung-Jr Jan
IPC分类号： G09G3/20 , G09G5/39 , G06F13/00
CPC分类号： G09G3/2092 , G09G3/3611 , G09G5/42
摘要： A data access method for a timing controller of a flat panel display includes forming a line buffer including a plurality of memory cells in the timing controller, dividing the plurality of memory cells into a first section and a second section, wherein the number of memory cells in the first section is greater than the number of memory cells in the second section, writing a first number of pixel data into the first section, wherein the first number of pixel data is included in a plurality of pixel data corresponding to a row of a frame, writing a second number of pixel data into the second section, wherein the second number of pixel data is included in the plurality of pixel data, and the first number is equal to the second number, and reading the plurality of pixel data from the plurality of memory cells according to an order.
摘要翻译：用于平板显示器的定时控制器的数据存取方法包括在定时控制器中形成包括多个存储单元的行缓冲器，将多个存储单元分成第一部分和第二部分，其中存储单元的数量在第一部分中大于第二部分中的存储器单元的数量，将第一数量的像素数据写入第一部分，其中第一数量的像素数据被包括在对应于一行的像素数据的多个像素数据中在所述第二部分中写入第二数量的像素数据，其中所述第二数量的像素数据被包括在所述多个像素数据中，并且所述第一数目等于所述第二数量，并且从所述第二数量读取所述多个像素数据多个存储单元。

3. 发明申请

US20090262840A1 Synchronization Signal Extraction Device and Related Method 审中-公开
标题翻译：同步信号提取装置及相关方法
公开(公告)号：US20090262840A1
公开(公告)日：2009-10-22
申请号：US12181325
申请日：2008-07-29
申请人： Chung-Jr Jan , Shang-Hsiu Wu , Kuo-Chi Chen , Ying-Jie Su , Po-Jui Huang , Chien-Cheng Tu , Po-Ju Lee
发明人： Chung-Jr Jan , Shang-Hsiu Wu , Kuo-Chi Chen , Ying-Jie Su , Po-Jui Huang , Chien-Cheng Tu , Po-Ju Lee
IPC分类号： H04N7/26
CPC分类号： H04N5/08 , G09G3/2092 , G09G5/006 , G09G2310/065 , G09G2320/0204 , G09G2320/0223 , H04N5/04
摘要： A synchronization signal extraction device includes a signal reception terminal for receiving a composite video signal, a threshold voltage adjuster coupled to the signal reception terminal for adjusting a threshold voltage to a ratio of a first characteristic level and a second characteristic level of the composite video signal according to the first characteristic level and the second characteristic level, a slicer coupled to the signal reception terminal and the threshold voltage adjuster for slicing the composite video signal to extract a synchronization signal in the composite video signal, and a signal output terminal coupled to the slicer for outputting the extracted synchronization signal.
摘要翻译：同步信号提取装置包括用于接收复合视频信号的信号接收端子，耦合到信号接收端的阈值电压调节器，用于将阈值电压调整为复合视频信号的第一特征电平和第二特性电平的比率根据第一特征电平和第二特性电平，耦合到信号接收端的限幅器和阈值电压调节器，用于对复合视频信号进行分片以提取复合视频信号中的同步信号;以及信号输出端，耦合到限幅器，用于输出所提取的同步信号。

4. 发明申请

US20090251477A1 MEMORY SAVING DISPLAY DEVICE 审中-公开
标题翻译：内存保存显示设备
公开(公告)号：US20090251477A1
公开(公告)日：2009-10-08
申请号：US12175449
申请日：2008-07-17
申请人： Ying-Jie Su , Po-Jui Huang , Chung-Jr Jan , Yu-Lin Cheng
发明人： Ying-Jie Su , Po-Jui Huang , Chung-Jr Jan , Yu-Lin Cheng
IPC分类号： G09G5/36
CPC分类号： G09G3/3611 , G09G2320/0252 , G09G2340/02 , G09G2340/16
摘要： A display device capable of saving memory storage used for an overdriving function includes a compression unit, a frame buffer, a decompression unit and a look-up table (LUT) unit. The compression unit includes a decimation filter and is used for compressing data of a received frame and reducing a size of the received frame, to generate a compression frame. The frame buffer is coupled to the compression unit and used for storing the compression frame. The decompression unit includes an interpolation filter and is used for decompressing data of the compression frame outputted by the frame buffer and reducing a size of the compression frame, to generate a decompression frame. The LUT unit is coupled to the decompression unit and used for comparing the decompression frame with a next received frame of the received frame to determine an overdriving voltage.
摘要翻译：能够节省用于过驱动功能的存储器存储的显示装置包括压缩单元，帧缓冲器，解压缩单元和查找表（LUT）单元。压缩单元包括抽取滤波器，用于压缩接收到的帧的数据并减小接收帧的大小，以产生压缩帧。帧缓冲器耦合到压缩单元并用于存储压缩帧。解压缩单元包括内插滤波器，用于对由帧缓冲器输出的压缩帧的数据进行解压缩并减小压缩帧的大小，生成解压缩帧。 LUT单元耦合到解压缩单元，用于将解压缩帧与接收帧的下一个接收帧进行比较，以确定过驱动电压。

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