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    • 3. 发明申请
    • HALF WIDTH COUNTING LEADING ZERO CIRCUIT USING COMPARATORS
    • 使用比较器的半宽度计数引线零电路
    • US20130332788A1
    • 2013-12-12
    • US13489551
    • 2012-06-06
    • Deepak K. Singh
    • Deepak K. Singh
    • H03M13/03G06F11/10
    • G06F7/74
    • A circuit and method are provided for providing a value representing the number of leading zero bits in an input data word. The input data word contains random data. The input data word is logically divided into odd and even bit positions. The circuit includes a first comparator circuit comparing data in the odd bit positions to data in the even bit positions. The circuit further includes a second comparator circuit comparing the data in the odd bit positions to a result of a logical operation performed on the data in the odd and even bit positions. The circuit further includes a half-width leading zero counting circuit that provides the value representing the number of leading zero bits in the input data word. The comparator circuits provide a correction bit value concatenated to the value.
    • 提供一种用于提供表示输入数据字中的前导零比特数的值的电路和方法。 输入数据字包含随机数据。 输入数据字在逻辑上分为奇数位和偶位位。 电路包括将奇数位位置中的数据与偶数位位置中的数据进行比较的第一比较器电路。 电路还包括第二比较器电路,将奇数位位置中的数据与对奇数位和偶位位数据执行的逻辑运算结果进行比较。 该电路还包括一个半宽度的前置零计数电路,其提供表示输入数据字中的前导零比特数的值。 比较器电路提供连接到该值的校正位值。
    • 4. 发明申请
    • Expanded Scope Incrementer
    • 扩展范围递增器
    • US20130290393A1
    • 2013-10-31
    • US13926918
    • 2013-06-25
    • Deepak K. Singh
    • Deepak K. Singh
    • G06F7/505
    • G06F7/5055
    • An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word.
    • 提供了一种用于递增的递增器电路和方法,其通过将输入数据字幅度增加到几个整数值之一来计算输出数据字。 增量器电路包括模式增量信号电路,其提供用于增加输入数据字幅度的整数值之一的指定。 单个常数增量器连接到模式增量信号电路和输入数据字,并通过选择性地向输入数据字添加常数来提供中间和。 多路复用电路将所选择的输入数据字位位置值与形成逻辑位位置值的模式增量信号电路指定逻辑组合,并将所选择的输入数据字位位置值,所选择的逻辑位位置值和中间和的选定位位置值引导到 形成输出数据字。
    • 5. 发明授权
    • Temperature dependent voltage source compensation
    • 温度依赖电压源补偿
    • US08022685B2
    • 2011-09-20
    • US11671568
    • 2007-02-06
    • Deepak K. SinghFrancois Ibrahim Atallah
    • Deepak K. SinghFrancois Ibrahim Atallah
    • G05F1/56G05F1/565G05F1/567
    • G06F1/26Y10S323/907
    • A circuit and a method for regulating a voltage supply where the method includes the steps of concurrently measuring temperature, IR drop and frequency response within the circuit, adjusting voltage supplied to the circuit in response to the measured temperature, IR drop and frequency response, and determining a correction value based on the variance of the measured frequency response from an expected frequency response and providing a correction for subsequent predetermined frequency response values. The frequency response measurement is dependent upon the constant bandgap voltage source which may very according to temperature. Upon a determination that corrections may be required for the bandgap voltage source to compensate for temperature variations, the measurement process which uses the bandgap voltage source can be altered to compensate for the temperature variations.
    • 一种用于调节电压源的电路和方法,其中该方法包括同时测量电路内的温度,IR降低和频率响应的步骤,响应于测量的温度,IR降低和频率响应调整提供给电路的电压,以及 基于来自预期频率响应的所测量的频率响应的方差来确定校正值,并为随后的预定频率响应值提供校正。 频率响应测量取决于可能非常根据温度的恒定带隙电压源。 在确定带隙电压源可能需要校正以补偿温度变化的情况下,可以改变使用带隙电压源的测量过程以补偿温度变化。
    • 7. 发明授权
    • Half width counting leading zero circuit
    • 半宽度计数导通零电路
    • US08005880B2
    • 2011-08-23
    • US11844402
    • 2007-08-24
    • Deepak K. SinghScott Michael McCluskey
    • Deepak K. SinghScott Michael McCluskey
    • G06F7/00G06F15/00
    • G06F7/74
    • A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most significant bit position. The data word is examined to determine the number of consecutive bits having the same numeric value. The invention first corrects for any single bit anomaly within the consecutive equal value sequence, counts the number of consecutive bits having this equal value using logic that examines only every other bit position of the stored data word and provides a numeric value representing this number of consecutive equal value bits.
    • 提供了一种电路和方法,用于将数据字存储在锁存器中并确定数据字内的连续相等值位的数目。 数据字由存储在唯一位位置并具有最低有效位位置和最高有效位位置的位组成。 检查数据字以确定具有相同数值的连续位的数量。 本发明首先校正连续等值序列内的任何单个位异常,使用仅检查所存储的数据字的每隔一个比特位置的逻辑来计数具有该相等值的连续比特的数量,并提供表示该数目的连续的数量的数值 等值位。
    • 9. 发明授权
    • Expanded scope incrementor
    • 扩展范围增量器
    • US08554821B2
    • 2013-10-08
    • US12852660
    • 2010-08-09
    • Deepak K. Singh
    • Deepak K. Singh
    • G06F7/50
    • G06F7/5055
    • An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word.
    • 提供了一种用于递增的递增器电路和方法,其通过将输入数据字幅度增加到几个整数值之一来计算输出数据字。 增量器电路包括模式增量信号电路,其提供用于增加输入数据字幅度的整数值之一的指定。 单个常数增量器连接到模式增量信号电路和输入数据字,并通过选择性地向输入数据字添加常数来提供中间和。 多路复用电路将所选择的输入数据字位位置值与形成逻辑位位置值的模式增量信号电路指定逻辑组合,并将所选择的输入数据字位位置值,所选择的逻辑位位置值和中间和的选定位位置值引导到 形成输出数据字。