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1. 发明授权

US07499962B2 Enhanced fused multiply-add operation 有权
标题翻译：增强融合乘法运算
公开(公告)号：US07499962B2
公开(公告)日：2009-03-03
申请号：US11019921
申请日：2004-12-21
申请人： Ping T. Tang , David D. Donofrio
发明人： Ping T. Tang , David D. Donofrio
IPC分类号： G06F7/483
CPC分类号： G06F7/5443 , G06F7/483
摘要： An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first adder to generate S1, where S1 is the sum of an integer k, the exponent of a floating point value A, and the exponent of a floating point value B. The exponent unit also includes a comparator to generate E1, where E1 is the greater of S1 and the exponent of a floating point value C. The apparatus also includes a partial multiplier, a shifter, and a second adder. The partial multiplier generates the partial products of the mantissas of A and B. The shifter aligns the partial products and the mantissa of C, based on E1. The second adder adds the aligned partial products and the mantissa of C. The apparatus is able to generate not only (A*B+C), but is enhanced to also be able to generate (2k*A*B+C) and the closest integer to (2k*A*B) in two's complement or floating point format.
摘要翻译：公开了一种用于执行增强的融合乘法运算的装置，方法和系统。在一个实施例中，装置包括指数单元。指数单元包括产生S1的第一加法器，其中S1是整数k，浮点值A的指数和浮点值B的指数之和。指数单元还包括产生E1的比较器其中E1是S1中的较大者和浮点值C的指数。该装置还包括部分乘法器，移位器和第二加法器。部分乘法器产生A和B的尾数的部分乘积。移位器基于E1对齐部分乘积和C的尾数。第二个加法器将对齐的部分积和C的尾数相加。该装置能够不仅产生（A * B + C），而且能够增强也能够生成（2k * A * B + C）和最接近的整数（2k * A * B）为二进制补码或浮点格式。

2. 发明授权

US07126798B2 On die voltage regulator 有权
标题翻译：在电压调节器上
公开(公告)号：US07126798B2
公开(公告)日：2006-10-24
申请号：US10889515
申请日：2004-07-12
申请人： Michael D. Piorun , Andrew Volk , Chinnugounder Senthilkumar , Robert Fulton , David D. Donofrio , Steve S. Simoni
发明人： Michael D. Piorun , Andrew Volk , Chinnugounder Senthilkumar , Robert Fulton , David D. Donofrio , Steve S. Simoni
IPC分类号： H02H3/22
CPC分类号： G05F1/56 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, an integrated circuit (IC) is disclosed. The IC includes a package, a die mounted within the package, circuit components mounted on the die, and a voltage regulator mounted on the die to supply power to the circuit components.
摘要翻译：根据一个实施例，公开了集成电路（IC）。 IC包括封装，安装在封装内的管芯，安装在管芯上的电路部件和安装在管芯上的电压调节器，以向电路部件供电。

3. 发明授权

US06940163B2 On die voltage regulator 有权
标题翻译：在电压调节器上
公开(公告)号：US06940163B2
公开(公告)日：2005-09-06
申请号：US10334505
申请日：2002-12-31
申请人： Michael D. Piorun , Andrew Volk , Chinnugounder Senthilkumar , Robert Fulton , David D. Donofrio , Steve S. Simoni
发明人： Michael D. Piorun , Andrew Volk , Chinnugounder Senthilkumar , Robert Fulton , David D. Donofrio , Steve S. Simoni
IPC分类号： G05F1/56 , G11C8/02 , H01L23/02 , H01L23/34
CPC分类号： G05F1/56 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, an integrated circuit (IC) is disclosed. The IC includes a package, a die mounted within the package, circuit components mounted on the die, and a voltage regulator mounted on the die to supply power to the circuit components.
摘要翻译：根据一个实施例，公开了集成电路（IC）。 IC包括封装，安装在封装内的管芯，安装在管芯上的电路部件和安装在管芯上的电压调节器，以向电路部件供电。

4. 发明授权

US07765386B2 Scalable parallel pipeline floating-point unit for vector processing 有权
标题翻译：用于矢量处理的可扩展并行流水线浮点单元
公开(公告)号：US07765386B2
公开(公告)日：2010-07-27
申请号：US11237548
申请日：2005-09-28
申请人： David D. Donofrio , Michael Dwyer
发明人： David D. Donofrio , Michael Dwyer
IPC分类号： G06F9/00
CPC分类号： G06F9/3885 , G06F9/3851 , G06F15/8061
摘要： An embodiment of the present invention is a technique to perform floating-point operations for vector processing. An input queue captures a plurality of vector inputs. A scheduler dispatches the vector inputs. A plurality of floating-point (FP) pipelines generates FP results from operating on scalar components of the vector inputs dispatched from the scheduler. An arbiter and assembly unit arbitrates use of output section and assembles the FP results to write to the output section.
摘要翻译：本发明的一个实施例是用于执行向量处理的浮点运算的技术。输入队列捕获多个向量输入。调度器调度向量输入。多个浮点（FP）流水线从对调度器调度的向量输入的标量分量进行操作生成FP结果。仲裁器和装配单元仲裁使用输出部分并组装FP结果以写入输出部分。

5. 发明授权

US07676535B2 Enhanced floating-point unit for extended functions 有权
标题翻译：用于扩展功能的增强型浮点单元
公开(公告)号：US07676535B2
公开(公告)日：2010-03-09
申请号：US11236984
申请日：2005-09-28
申请人： David D. Donofrio , Xuye Li
发明人： David D. Donofrio , Xuye Li
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/535 , G06F2207/5355
摘要： An embodiment of the present invention is a technique to perform floating-point operations. A floating-point (FP) squarer squares a first argument to produce an intermediate argument. The first and intermediate arguments have first and intermediate mantissas and exponents. A FP multiply-add (MAD) unit performs a multiply-and-add operation on the intermediate argument, a second argument, and a third argument to produce a result having a result mantissa and a result exponent. The second and third arguments have second and third mantissas and exponents, respectively.
摘要翻译：本发明的实施例是执行浮点运算的技术。浮点（FP）正方形对齐第一个参数以产生中间参数。第一个和中间的论点有第一个和中间的尾随和指数。 FP乘法（MAD）单元对中间参数，第二参数和第三参数执行乘法和加法运算，以产生具有结果尾数和结果指数的结果。第二和第三个论点分别有第二和第三个尾声和指数。

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