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1. 发明申请

US20100327314A1 Insulated Gate Bipolar Transistor (IGBT) Collector Formed with Ge/A1 and Production Method 审中-公开
标题翻译：绝缘栅双极晶体管（IGBT）采用Ge / A1及其制作方法
公开(公告)号：US20100327314A1
公开(公告)日：2010-12-30
申请号：US12493226
申请日：2009-06-28
申请人： Ping Huang , Tao Feng , Ruisheng Wu , Yi Chen , Lei Duan
发明人： Ping Huang , Tao Feng , Ruisheng Wu , Yi Chen , Lei Duan
IPC分类号： H01L29/739 , H01L21/20
CPC分类号： H01L29/7395 , H01L29/0834 , H01L29/165 , H01L29/66333
摘要： This invention discloses an IGBT device with its collector formed with Ge/Al and associated method of fabrication. The collector is formed on the substrate layer, which is on the back of IGBT, and contains Ge and Al thin films. After thinning and etching the back side of IGBT substrate, Ge and Al are sequentially deposited to form Ge/Al thin films on the back surface of the substrate. An annealing process is then carried out to diffuse Al into Ge thin film layer to form a P-doped Ge layer functioning as the IGBT collector. The present invention is applicable to both non punch through IGBTs as well as punch through IGBTs.
摘要翻译：本发明公开了一种IGBT器件，其集电极形成Ge / Al及其制造方法。集电体形成在IGBT背面的基板层上，并含有Ge和Al薄膜。在对IGBT基板的背面进行变薄蚀刻之后，依次沉积Ge和Al，以在衬底的背面形成Ge / Al薄膜。然后进行退火处理以将Al扩散到Ge薄膜层中，以形成用作IGBT集电极的P掺杂Ge层。本发明适用于非穿通IGBT以及穿通IGBT。

2. 发明申请

US20120104580A1 SUBSTRATELESS POWER DEVICE PACKAGES 有权
标题翻译：无底座动力装置包装
公开(公告)号：US20120104580A1
公开(公告)日：2012-05-03
申请号：US12916086
申请日：2010-10-29
申请人： Tao Feng , Zhiqiang Niu , Yuping Gong , Ruisheng Wu , Ping Huang , Lei Shi , Yueh-Se Ho
发明人： Tao Feng , Zhiqiang Niu , Yuping Gong , Ruisheng Wu , Ping Huang , Lei Shi , Yueh-Se Ho
IPC分类号： H01L23/495 , H01L23/498
CPC分类号： H01L21/6836 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/76897 , H01L21/78 , H01L23/3114 , H01L23/481 , H01L23/495 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/36 , H01L24/40 , H01L24/73 , H01L24/94 , H01L25/50 , H01L27/088 , H01L29/0657 , H01L29/7827 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04026 , H01L2224/04034 , H01L2224/05009 , H01L2224/05025 , H01L2224/051 , H01L2224/05139 , H01L2224/05155 , H01L2224/05166 , H01L2224/05571 , H01L2224/0603 , H01L2224/0616 , H01L2224/06181 , H01L2224/1184 , H01L2224/16245 , H01L2224/291 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/73253 , H01L2224/73255 , H01L2224/73263 , H01L2224/83801 , H01L2224/84801 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10253 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/2064 , H01L2924/3511 , H01L2224/03 , H01L2924/00 , H01L2224/05552 , H01L2924/00012 , H01L2224/37099
摘要： A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
摘要翻译：无基底复合功率半导体器件可以包括薄衬底和位于衬底顶表面上的顶金属层。衬底和外延层的总厚度可以小于25微米。焊料凸块形成在顶部金属层的顶部，并且模塑料围绕焊料凸起并且使焊料凸块至少部分暴露。

3. 发明授权

US08987878B2 Substrateless power device packages 有权
标题翻译：无层无源功率器件封装
公开(公告)号：US08987878B2
公开(公告)日：2015-03-24
申请号：US12916086
申请日：2010-10-29
申请人： Tao Feng , Zhiqiang Niu , Yuping Gong , Ruisheng Wu , Ping Huang , Lei Shi , Yueh-Se Ho
发明人： Tao Feng , Zhiqiang Niu , Yuping Gong , Ruisheng Wu , Ping Huang , Lei Shi , Yueh-Se Ho
IPC分类号： H01L23/495 , H01L21/683 , H01L21/56 , H01L23/31 , H01L23/48 , H01L23/00 , H01L29/06
CPC分类号： H01L21/6836 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/76897 , H01L21/78 , H01L23/3114 , H01L23/481 , H01L23/495 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/36 , H01L24/40 , H01L24/73 , H01L24/94 , H01L25/50 , H01L27/088 , H01L29/0657 , H01L29/7827 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04026 , H01L2224/04034 , H01L2224/05009 , H01L2224/05025 , H01L2224/051 , H01L2224/05139 , H01L2224/05155 , H01L2224/05166 , H01L2224/05571 , H01L2224/0603 , H01L2224/0616 , H01L2224/06181 , H01L2224/1184 , H01L2224/16245 , H01L2224/291 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/73253 , H01L2224/73255 , H01L2224/73263 , H01L2224/83801 , H01L2224/84801 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10253 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/2064 , H01L2924/3511 , H01L2224/03 , H01L2924/00 , H01L2224/05552 , H01L2924/00012 , H01L2224/37099
摘要： A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
摘要翻译：无基底复合功率半导体器件可以包括薄衬底和位于衬底顶表面上的顶金属层。衬底和外延层的总厚度可以小于25微米。焊料凸块形成在顶部金属层的顶部，并且模塑料围绕焊料凸起并且使焊料凸块至少部分暴露。

4. 发明授权

US07842543B2 Wafer level chip scale package and method of laser marking the same 有权
标题翻译：晶圆级芯片级封装和激光打标方法相同
公开(公告)号：US07842543B2
公开(公告)日：2010-11-30
申请号：US12378713
申请日：2009-02-17
申请人： Ruisheng Wu , Yan Liu , Tao Feng
发明人： Ruisheng Wu , Yan Liu , Tao Feng
IPC分类号： H01L21/50
CPC分类号： H01L23/544 , H01L21/67282 , H01L2223/54406 , H01L2223/54433 , H01L2223/54473 , H01L2223/54486 , H01L2224/274 , H01L2924/01079 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091
摘要： A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer.
摘要翻译：公开了一种晶片级芯片级封装及其激光标记方法。该方法包括在晶片的前表面上形成多个半导体器件，金属化器件接触晶片的前侧表面，研磨晶片的背面，硅蚀刻晶片的背面，激光标记背面在所述硅蚀刻步骤之后的所述晶片的氧化物，在所述激光标记步骤之后，氧化物蚀刻所述晶片的所述背面，在所述氧化物蚀刻步骤之后，在所述晶片的所述背面表面上沉积金属层，以及将所述晶片切割成晶片级芯片级封装。晶片级芯片级封装包括在其背面形成的标记，该标记包括形成在硅背面中的多个沟槽和形成在覆盖背面金属层中的相应凹痕。

5. 发明申请

US20100207283A1 Wafer level chip scale package and method of laser marking the same 有权
标题翻译：晶圆级芯片级封装和激光打标方法相同
公开(公告)号：US20100207283A1
公开(公告)日：2010-08-19
申请号：US12378713
申请日：2009-02-17
申请人： Ruisheng Wu , Yan Liu , Tao Feng
发明人： Ruisheng Wu , Yan Liu , Tao Feng
IPC分类号： H01L21/304 , H01L23/544
CPC分类号： H01L23/544 , H01L21/67282 , H01L2223/54406 , H01L2223/54433 , H01L2223/54473 , H01L2223/54486 , H01L2224/274 , H01L2924/01079 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091
摘要： A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer
摘要翻译：公开了一种晶片级芯片级封装及其激光标记方法。该方法包括在晶片的前表面上形成多个半导体器件，金属化器件接触晶片的前侧表面，研磨晶片的背面，硅蚀刻晶片的背面，激光标记背面在所述硅蚀刻步骤之后的所述晶片的氧化物，在所述激光标记步骤之后，氧化物蚀刻所述晶片的所述背面，在所述氧化物蚀刻步骤之后，在所述晶片的所述背面表面上沉积金属层，以及将所述晶片切割成晶片级芯片级封装。晶片级芯片级封装包括在其背面形成的标记，标记包括形成在硅背面中的多个沟槽和形成在覆盖背面金属层中的相应凹痕

6. 发明授权

US09163035B2 Melonine bisindole compounds, pharmaceutical compositions, preparation method and use thereof 有权
标题翻译：甜菜双吲哚化合物，药物组合物，其制备方法和用途
公开(公告)号：US09163035B2
公开(公告)日：2015-10-20
申请号：US13508277
申请日：2010-11-04
申请人： Xiaodong Luo , Tao Feng , Yan Li , Yuanyuan Wang , Xianghai Cai , Yaping Liu
发明人： Xiaodong Luo , Tao Feng , Yan Li , Yuanyuan Wang , Xianghai Cai , Yaping Liu
IPC分类号： C07D519/04 , A61K31/4375 , A61K31/475 , A61K36/24 , C07D519/00
CPC分类号： C07D519/04 , A61K31/4375 , A61K31/475 , A61K36/24 , C07D519/00
摘要： The present invention relates to pharmaceutical technical field, to melonine bisindole compounds, pharmaceutical compositions thereof, and preparation methods thereof. Specifically, the present invention relates to melonine bisindole compounds of Formula I, pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising the compounds or pharmaceutically acceptable salts thereof. The present invention further relates to method for preparing the melonine bisindole compounds of Formula I or pharmaceutically acceptable salts thereof, and the use of the melonine bisindole compounds of Formula I or pharmaceutically acceptable salts thereof in the manufacture of a medicament for the treatment or prophylaxis of cancers.
摘要翻译：本发明涉及药用技术领域，甜瓜双吲哚化合物及其药物组合物及其制备方法。具体地，本发明涉及式I的甜瓜双吲哚化合物，其药学上可接受的盐，包含该化合物或其药学上可接受的盐的药物组合物。本发明还涉及制备式I的甜菜双吲哚化合物或其药学上可接受的盐的方法，以及式I的甜瓜双吲哚化合物或其药学上可接受的盐在制备用于治疗或预防癌症

7. 发明授权

US08866267B2 Semiconductor device with substrate-side exposed device-side electrode and method of fabrication 有权
标题翻译：具有基板侧暴露的器件侧电极的半导体器件及其制造方法
公开(公告)号：US08866267B2
公开(公告)日：2014-10-21
申请号：US12790773
申请日：2010-05-28
申请人： Tao Feng , Anup Bhalla
发明人： Tao Feng , Anup Bhalla
IPC分类号： H01L29/40 , H01L29/78 , H01L29/423 , H01L29/66 , H01L23/48 , H01L29/06 , H01L23/00 , H01L29/417
CPC分类号： H01L23/49844 , H01L23/481 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L29/41741 , H01L29/42372 , H01L29/66734 , H01L29/781 , H01L29/7813 , H01L29/7827 , H01L2224/04042 , H01L2224/0557 , H01L2224/05571 , H01L2224/0603 , H01L2224/06051 , H01L2224/06102 , H01L2224/29006 , H01L2224/29007 , H01L2224/32245 , H01L2224/45014 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/49107 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/05552 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE.
摘要翻译：公开了一种具有基板侧暴露的器件侧电极（SEDE）的半导体器件。半导体器件在器件侧具有器件侧，衬底侧和半导体器件区（SDR）的半导体衬底（SCS）。形成器件侧电极（DSE）用于器件操作。通过衬底沟槽（TST）延伸通过SCS，达到DSE将其变成SEDE。 SEDE可以通过TST通过导电互连器相互连接。可以包括在SSE上面的衬底侧电极（SSE）和窗口化的衬底侧钝化（SSPV）。 SSPV定义了在设备封装期间扩展焊料材料的SSE区域。可以包括下面覆盖SEDE的器件侧的器件侧钝化（DSPV）。 DSE还可以包括在SEDE下面堆叠的扩展支撑凸缘，用于在晶片间加工包装期间对其进行结构支持。延伸支撑突出到主SCS平面上的预计占地面积基本上可以包围SEDE相应的预计占地面积。

8. 发明授权

US08466060B2 Stackable power MOSFET, power MOSFET stack, and process of manufacture 有权
标题翻译：可堆叠功率MOSFET，功率MOSFET堆栈和制造工艺
公开(公告)号：US08466060B2
公开(公告)日：2013-06-18
申请号：US12772048
申请日：2010-04-30
申请人： Tao Feng
发明人： Tao Feng
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/3107 , H01L21/6836 , H01L23/481 , H01L23/4824 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/48 , H01L24/94 , H01L25/074 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/05552 , H01L2224/05554 , H01L2224/0557 , H01L2224/0603 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/32245 , H01L2224/40095 , H01L2224/40247 , H01L2224/48227 , H01L2224/48247 , H01L2224/81894 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2225/0651 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12041 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： A thin and stackable power MOSFET (SP-MOSFET) and method are proposed. The SVP-MOSFET includes semiconductor substrate with bottom drain metal layer. Formed atop the semiconductor substrate are trenched gate regions and source-body regions. A patterned gate metal layer and source-body metal layer respectively contact trenched gate regions and source-body regions. At least one of through substrate drain via (TSDV), through substrate gate via (TSGV), through substrate source via (TSSV) is provided. The TSDV, formed through semiconductor substrate and in contact with drain metal layer, has top drain contacting pad and bottom drain contacting pad for making top and bottom contacts thereto. Similarly the TSGV, formed through semiconductor substrate and in contact with gate metal layer, has top gate contacting pad and bottom gate contacting pad. Likewise the TSSV, formed through semiconductor substrate and in contact with source-body metal layer, has top source contacting pad and bottom source contacting pad.
摘要翻译：提出了一种薄型和可堆叠功率MOSFET（SP-MOSFET）和方法。 SVP-MOSFET包括具有底部漏极金属层的半导体衬底。形成在半导体衬底顶部的是沟槽栅区和源体区。图案化栅极金属层和源体金属层分别接触沟槽栅极区域和源极体区域。提供贯穿衬底漏极通孔（TSDV），衬底栅极通孔（TSGV），衬底源极通孔（TSSV）中的至少一个。通过半导体衬底形成并与漏极金属层接触的TSDV具有顶部漏极接触焊盘和底部漏极接触焊盘，用于与其接触。类似地，通过半导体衬底形成并与栅极金属层接触的TSGV具有顶栅接触焊盘和底栅接触焊盘。同样地，通过半导体衬底形成并与源体金属层接触的TSSV具有顶部源接触焊盘和底部源接触焊盘。

9. 发明授权

US08461004B2 Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling 有权
标题翻译：配置高压半导体功率器件实现三维电荷耦合
公开(公告)号：US08461004B2
公开(公告)日：2013-06-11
申请号：US13066373
申请日：2011-04-12
申请人： François Hébert , Tao Feng
发明人： François Hébert , Tao Feng
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/66712 , H01L29/7395 , H01L29/7803 , H01L29/861 , H01L29/872
摘要： This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.
摘要翻译：本发明公开了一种半导体器件，其包括顶部区域和底部区域，其中间区域设置在所述顶部区域和所述底部区域之间，并具有穿过所述中间区域的可控电流通路。所述半导体器件还包括沟槽，该沟槽在从所述顶部区域延伸穿过所述中间区域朝向所述底部区域的侧壁上被填充有绝缘层，其中所述沟槽包括随机均匀分布的纳米结节，作为与下面的漏极区域接触的电荷岛用于与中间区域电耦合的沟槽，用于通过电流路径连续均匀地分配电压降。

10. 发明授权

US08450151B1 Micro surface mount device packaging 有权
标题翻译：微表面贴装装置包装
公开(公告)号：US08450151B1
公开(公告)日：2013-05-28
申请号：US13303053
申请日：2011-11-22
申请人： Anindya Poddar , Tao Feng , Will K. Wong
发明人： Anindya Poddar , Tao Feng , Will K. Wong
IPC分类号： H01L23/08 , H01L23/488 , H01L23/28
CPC分类号： H01L24/19 , H01L21/561 , H01L21/568 , H01L23/13 , H01L23/145 , H01L23/3114 , H01L23/49816 , H01L23/5389 , H01L24/97 , H01L2223/6677 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/12042 , H01L2924/15153 , H01L2224/83 , H01L2924/00
摘要： A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages.
摘要翻译：描述了用于封装集成电路的各种改进方法。在所描述的方法中，多个骰子安装在载体（例如，塑料载体）上。每个管芯具有固定到其相关联的I / O焊盘的多个引线接合柱塞。在载体上施加密封剂以覆盖骰子和至少部分接触柱以形成密封剂载体结构。在施加了密封剂之后，密封剂的第一表面和接触柱被研磨，使得接触柱的暴露部分与密封剂平滑并且基本上共面。在一些实施例中，在密封剂载体结构上方形成再分配层，并且焊料凸块附着到再分配层。接触密封剂层施加在密封剂载体结构上以为所得到的包装提供额外的机械支撑。

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