专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07456093B2 Method for improving a semiconductor device delamination resistance 有权
标题翻译：提高半导体器件耐分层性的方法
公开(公告)号：US07456093B2
公开(公告)日：2008-11-25
申请号：US10884719
申请日：2004-07-03
申请人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
发明人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/3135 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要翻译：具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

2. 发明申请

US20060003572A1 Method for improving a semiconductor device delamination resistance 有权
标题翻译：提高半导体器件耐分层性的方法
公开(公告)号：US20060003572A1
公开(公告)日：2006-01-05
申请号：US10884719
申请日：2004-07-03
申请人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
发明人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/3135 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要翻译：具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

3. 发明授权

US07223692B2 Multi-level semiconductor device with capping layer for improved adhesion 有权
标题翻译：具有覆盖层的多层半导体器件，用于改善粘附力
公开(公告)号：US07223692B2
公开(公告)日：2007-05-29
申请号：US10836297
申请日：2004-04-30
申请人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
发明人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/447 , H01L21/4763
CPC分类号： H01L21/76826 , H01L21/76825 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multi-layer semiconductor device including copper interconnects with improved interlayer adhesion and a method for forming the same, the method including providing a semiconductor substrate comprising a dielectric insulating layer comprising copper containing interconnects the dielectric insulating layer and copper containing interconnects comprising an exposed surface; forming a first capping layer on the exposed surface; providing a treatment on the first capping layer to increase interface adhesion between the capping layer and the dielectric insulating layer; and, forming a second capping layer on the first capping layer.
摘要翻译：一种包括具有改进的层间粘合性的铜互连的多层半导体器件及其形成方法，所述方法包括提供半导体衬底，所述半导体衬底包括包含铜的介电绝缘层，所述电介质绝缘层将所述介电绝缘层和包含暴露表面的含铜互连互连; 在所述暴露表面上形成第一覆盖层; 在所述第一盖层上提供处理以增加所述封盖层和所述介电绝缘层之间的界面粘附; 并且在所述第一覆盖层上形成第二覆盖层。

4. 发明申请

US20050242430A1 Multi-level semiconductor device with capping layer with improved adhesion 有权
标题翻译：具有覆盖层的多层半导体器件具有改善的附着力
公开(公告)号：US20050242430A1
公开(公告)日：2005-11-03
申请号：US10836297
申请日：2004-04-30
申请人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
发明人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/532 , H01L29/40
CPC分类号： H01L21/76826 , H01L21/76825 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multi-layer semiconductor device including copper interconnects with improved interlayer adhesion and a method for forming the same, the method including providing a semiconductor substrate comprising a dielectric insulating layer comprising copper containing interconnects the dielectric insulating layer and copper containing interconnects comprising an exposed surface; forming a first capping layer on the exposed surface; providing a treatment on the first capping layer to increase interface adhesion between the capping layer and the dielectric insulating layer; and, forming a second capping layer on the first capping layer.
摘要翻译：一种包括具有改进的层间粘合性的铜互连的多层半导体器件及其形成方法，所述方法包括提供半导体衬底，所述半导体衬底包括包含铜的介电绝缘层，所述电介质绝缘层将所述介电绝缘层和包含暴露表面的含铜互连互连; 在所述暴露表面上形成第一覆盖层; 在所述第一盖层上提供处理以增加所述封盖层和所述介电绝缘层之间的界面粘附; 并且在所述第一覆盖层上形成第二覆盖层。

5. 发明申请

US20050062164A1 Method for improving time dependent dielectric breakdown lifetimes 审中-公开
标题翻译：改善时间依赖介电击穿寿命的方法
公开(公告)号：US20050062164A1
公开(公告)日：2005-03-24
申请号：US10668702
申请日：2003-09-23
申请人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
发明人： Keng-Chu Lin , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L29/06 , H01L29/40 , H01L29/00
CPC分类号： H01L21/76825 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/022 , H01L21/02304 , H01L21/02315 , H01L21/02351 , H01L21/3121 , H01L21/31633 , H01L21/3185 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L29/405
摘要： The present disclosure provides a method for increasing a time dependent dielectric breakdown lifetime of a semiconductor device and a structure fabricated using this method. The method includes depositing a first layer and then forming a glue layer on the first layer. A treatment process, which may use a plasma or an electron beam, is performed on the glue layer. The treatment process improves an interface between the glue layer and the first layer. The treatment process may also affect electrical properties of the glue layer. A second layer may then be deposited onto the treated glue layer.
摘要翻译：本公开提供了一种用于增加半导体器件的时间依赖介电击穿寿命和使用该方法制造的结构的方法。该方法包括沉积第一层然后在第一层上形成胶层。在胶层上进行可以使用等离子体或电子束的处理工艺。处理过程改善了胶层和第一层之间的界面。处理过程也可能影响胶层的电性能。然后可以将第二层沉积在经处理的胶层上。

6. 发明申请

US20080171431A1 Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
标题翻译：包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例
公开(公告)号：US20080171431A1
公开(公告)日：2008-07-17
申请号：US11654427
申请日：2007-01-17
申请人： Chen-Hua Yu , Yung-Cheng Lu , Pei-Ren Jeng , Chia-Cheng Chou , Keng-Chu Lin , Chung-Chi Ko , Tien-I Bao , Shwang-Ming Jeng
发明人： Chen-Hua Yu , Yung-Cheng Lu , Pei-Ren Jeng , Chia-Cheng Chou , Keng-Chu Lin , Chung-Chi Ko , Tien-I Bao , Shwang-Ming Jeng
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76835 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.
摘要翻译：提出了双层多孔低介电常数（低k）互连结构及其制造方法。具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积介电层和顶部沉积的介电层。底层和顶层具有相同的原子组成，但是较高的介电常数值k。底部介电层用作顶部电介质层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。固化过程在底部电介质层中留下比在顶部电介质层中留下的孔密度更低的孔密度，这导致底部电介质层中较高的介电值k。

7. 发明授权

US07723226B2 Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
标题翻译：包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例
公开(公告)号：US07723226B2
公开(公告)日：2010-05-25
申请号：US11654427
申请日：2007-01-17
申请人： Chen-Hua Yu , Yung-Cheng Lu , Pei-Ren Jeng , Chia-Cheng Chou , Keng-Chu Lin , Chung-Chi Ko , Tien-I Bao , Shwang-Ming Jeng
发明人： Chen-Hua Yu , Yung-Cheng Lu , Pei-Ren Jeng , Chia-Cheng Chou , Keng-Chu Lin , Chung-Chi Ko , Tien-I Bao , Shwang-Ming Jeng
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76835 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.
摘要翻译：提出了双层多孔低介电常数（低k）互连结构及其制造方法。具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。底层和顶层具有相同的原子组成，但是较高的介电常数值k。底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

8. 发明申请

US20070243720A1 UV treatment for low-k dielectric layer in damascene structure 有权
标题翻译：紫外线处理用于镶嵌结构中的低k电介质层
公开(公告)号：US20070243720A1
公开(公告)日：2007-10-18
申请号：US11404020
申请日：2006-04-14
申请人： Chung-Chi Ko , Keng-Chu Lin , Tien-I Bao
发明人： Chung-Chi Ko , Keng-Chu Lin , Tien-I Bao
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , H01L21/31058 , H01L21/76807 , H01L21/76814 , H01L21/76825
摘要： An UV treatment for making a low-k dielectric layer having improved properties in a damascene structure. A low-k dielectric layer in a damascene structure is subjected to an UV treatment with He gas or H2 gas to eliminate etching damage to the exposed surfaces of the low-k dielectric layer.
摘要翻译：用于制造具有改进的镶嵌结构性能的低k电介质层的UV处理。用Ho气体或H 2 O 2气体对镶嵌结构中的低k电介质层进行UV处理，以消除对低k电介质层的暴露表面的蚀刻损伤。

9. 发明申请

US20070202676A1 Integration scheme for cu/low-k interconnects 有权
标题翻译： cu / low-k互连的集成方案
公开(公告)号：US20070202676A1
公开(公告)日：2007-08-30
申请号：US11361331
申请日：2006-02-24
申请人： Ming Yeh , Chen-Hua Yu , Keng-Chu Lin , Tien-I Bao , Shwang-Ming Cheng
发明人： Ming Yeh , Chen-Hua Yu , Keng-Chu Lin , Tien-I Bao , Shwang-Ming Cheng
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02126 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/31633 , H01L21/31695 , H01L21/76808 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L21/76846
摘要： A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.
摘要翻译：提供了一种形成在多孔电介质层中的开口的半导体结构。沿着开口的侧壁的电介质层的暴露的孔被密封。密封可以包括选择性或非选择性沉积方法。密封层在开口的一部分中具有基本均匀的厚度，并且在开口的另一部分中具有不均匀的厚度。如其制造方法那样提供具有孔密封层的镶嵌互连结构。

10. 发明申请

US20060172531A1 Sealing pores of low-k dielectrics using CxHy 有权
标题翻译：使用CxHy密封低k电介质的孔隙
公开(公告)号：US20060172531A1
公开(公告)日：2006-08-03
申请号：US11048518
申请日：2005-02-01
申请人： Keng-Chu Lin , Shwang-Ming Cheng , Ming Yeh , Tien-I Bao
发明人： Keng-Chu Lin , Shwang-Ming Cheng , Ming Yeh , Tien-I Bao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831
摘要： A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing carbon depletion damage caused by plasma processing or etching. Surface dielectric pores damaged by plasma processing are also repaired by sealing them with the CXHY layer. Embodiments include semiconductor devices, such as devices having damascene interconnect structures, manufacturing using methods provided.
摘要翻译：提供了涉及含有多孔和/或碳的低k电介质的半导体制造方法。该方法包括在低k电介质的表面上形成总体组成为C H 的烃。烃层包括沉积前体材料，优选C 2 H 4 H 3或（CH 3 CH 3）2 CH 3， 6> 6 6 3。根据本发明的实施例，碳扩散到低k电介质中，从而减少由等离子体处理或蚀刻引起的碳损耗损伤。通过等离子体处理损坏的表面电介质孔也通过用C H 层密封来修复。实施例包括半导体器件，例如具有镶嵌互连结构的器件，使用提供的方法的制造。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式