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1. 发明申请

US20170036012A1 CONFORMALLY ENCAPSULATED MULTI-ELECTRODE ARRAYS WITH SEAMLESS INSULATION 审中-公开
标题翻译：具有无缝绝缘的均匀多孔电极阵列
公开(公告)号：US20170036012A1
公开(公告)日：2017-02-09
申请号：US15298140
申请日：2016-10-19
申请人： Phillipe J. Tabada , Satinderpall S. Pannu , Kedar G. Shah , Vanessa Tolosa , Angela Tooker , Terri Delima , Heeral Sheth , Sarah Felix
发明人： Phillipe J. Tabada , Satinderpall S. Pannu , Kedar G. Shah , Vanessa Tolosa , Angela Tooker , Terri Delima , Heeral Sheth , Sarah Felix
IPC分类号： A61N1/05 , A61B5/04
CPC分类号： A61N1/0551 , A61B5/04001 , A61B2562/046 , A61B2562/125 , A61K49/1806 , A61K51/1217 , A61N1/0529
摘要： Thin-film multi-electrode arrays (MEA) having one or more electrically conductive beams conformally encapsulated in a seamless block of electrically insulating material, and methods of fabricating such MEAs using reproducible, microfabrication processes. One or more electrically conductive traces are formed on scaffold material that is subsequently removed to suspend the traces over a substrate by support portions of the trace beam in contact with the substrate. By encapsulating the suspended traces, either individually or together, with a single continuous layer of an electrically insulating material, a seamless block of electrically insulating material is formed that conforms to the shape of the trace beam structure, including any trace backings which provide suspension support. Electrical contacts, electrodes, or leads of the traces are exposed from the encapsulated trace beam structure by removing the substrate.
摘要翻译：具有保形地封装在电绝缘材料的无缝块中的一个或多个导电梁的薄膜多电极阵列（MEA）以及使用可重复的微加工工艺制造这种MEA的方法。在支架材料上形成一个或多个导电迹线，其随后被移除，以通过与基底接触的迹线束的支撑部分将迹线悬置在基底上。通过将单独或一起的悬浮迹线与电绝缘材料的单个连续层封装，形成符合迹线结构的形状的无缝的电绝缘材料块，包括提供悬挂支撑的任何痕迹背衬。通过去除衬底，迹线的电触点，电极或引线从封装的迹线结构体露出。

2. 发明申请

US20130345780A1 Conformally Encapsulated Multi-Electrode Arrays With Seamless Insulation 有权
标题翻译：具有无缝绝缘的合适的多电极阵列
公开(公告)号：US20130345780A1
公开(公告)日：2013-12-26
申请号：US13792708
申请日：2013-03-11
申请人： Phillipe J. Tabada , Kedar G. Shah , Vanessa Tolosa , Satinderall S. Pannu , Angela Tooker , Terri Delima , Heeral Sheth , Sarah Felix
发明人： Phillipe J. Tabada , Kedar G. Shah , Vanessa Tolosa , Satinderall S. Pannu , Angela Tooker , Terri Delima , Heeral Sheth , Sarah Felix
IPC分类号： A61N1/04
CPC分类号： A61N1/0551 , A61B5/04001 , A61B2562/0209 , A61B2562/046 , A61B2562/125 , A61K8/044 , A61K49/1806 , A61K51/1217 , A61N1/04 , A61N1/0529
摘要： Thin-film multi-electrode arrays (MEA) having one or more electrically conductive beams conformally encapsulated in a seamless block of electrically insulating material, and methods of fabricating such MEAs using reproducible, microfabrication processes. One or more electrically conductive traces are formed on scaffold material that is subsequently removed to suspend the traces over a substrate by support portions of the trace beam in contact with the substrate. By encapsulating the suspended traces, either individually or together, with a single continuous layer of an electrically insulating material, a seamless block of electrically insulating material is formed that conforms to the shape of the trace beam structure, including any trace backings which provide suspension support. Electrical contacts, electrodes, or leads of the traces are exposed from the encapsulated trace beam structure by removing the substrate.
摘要翻译：具有保形地封装在电绝缘材料的无缝块中的一个或多个导电梁的薄膜多电极阵列（MEA）以及使用可重复的微加工工艺制造这种MEA的方法。在支架材料上形成一个或多个导电迹线，其随后被移除，以通过与基底接触的迹线束的支撑部分将迹线悬置在基底上。通过将单独或一起的悬浮迹线与电绝缘材料的单个连续层封装，形成符合迹线结构的形状的无缝的电绝缘材料块，包括提供悬挂支撑的任何痕迹背衬。通过去除衬底，迹线的电触点，电极或引线从封装的迹线结构体露出。

3. 发明授权

US09498617B2 Conformally encapsulated multi-electrode arrays with seamless insulation 有权
标题翻译：具有无缝绝缘的合适封装的多电极阵列
公开(公告)号：US09498617B2
公开(公告)日：2016-11-22
申请号：US13792708
申请日：2013-03-11
申请人： Melody Tabada , Kedar G. Shah , Vanessa Tolosa , Satinderall S. Pannu , Angela Tooker , Terri Delima , Heeral Sheth , Sarah Felix
发明人： Phillipe J. Tabada , Kedar G. Shah , Vanessa Tolosa , Satinderall S. Pannu , Angela Tooker , Terri Delima , Heeral Sheth , Sarah Felix
IPC分类号： A61N1/04 , A61N1/05 , A61K8/04 , A61K49/18 , A61K51/12 , A61B5/04
CPC分类号： A61N1/0551 , A61B5/04001 , A61B2562/0209 , A61B2562/046 , A61B2562/125 , A61K8/044 , A61K49/1806 , A61K51/1217 , A61N1/04 , A61N1/0529
摘要： Thin-film multi-electrode arrays (MEA) having one or more electrically conductive beams conformally encapsulated in a seamless block of electrically insulating material, and methods of fabricating such MEAs using reproducible, microfabrication processes. One or more electrically conductive traces are formed on scaffold material that is subsequently removed to suspend the traces over a substrate by support portions of the trace beam in contact with the substrate. By encapsulating the suspended traces, either individually or together, with a single continuous layer of an electrically insulating material, a seamless block of electrically insulating material is formed that conforms to the shape of the trace beam structure, including any trace backings which provide suspension support. Electrical contacts, electrodes, or leads of the traces are exposed from the encapsulated trace beam structure by removing the substrate.
摘要翻译：具有保形地封装在电绝缘材料的无缝块中的一个或多个导电梁的薄膜多电极阵列（MEA）以及使用可重复的微加工工艺制造这种MEA的方法。在支架材料上形成一个或多个导电迹线，其随后被移除，以通过与基底接触的迹线束的支撑部分将迹线悬置在基底上。通过将单独或一起的悬浮迹线与电绝缘材料的单个连续层封装，形成符合迹线结构的形状的无缝的电绝缘材料块，包括提供悬挂支撑的任何痕迹背衬。通过去除衬底，迹线的电触点，电极或引线从封装的迹线结构体露出。

4. 发明授权

US08183111B1 Method of fabricating conductive electrodes on the front and backside of a thin film structure 有权
标题翻译：在薄膜结构的正面和背面制造导电电极的方法
公开(公告)号：US08183111B1
公开(公告)日：2012-05-22
申请号：US12959232
申请日：2010-12-02
申请人： Phillipe J. Tabada , Melody Tabada, legal representative , Satinderpall S. Pannu
发明人： Phillipe J. Tabada , Satinderpall S. Pannu
IPC分类号： H01L21/336
CPC分类号： A61N1/0529 , H01L21/76814 , H05K1/11 , H05K3/4038 , H05K2201/0394
摘要： A method of fabricating a thin film device having conductive front and backside electrodes or contacts. Top-side cavities are first formed on a first dielectric layer, followed by the deposition of a metal layer on the first dielectric layer to fill the cavities. Defined metal structures are etched from the metal layer to include the cavity-filled metal, followed by depositing a second dielectric layer over the metal structures. Additional levels of defined metal structures may be formed in a similar manner with vias connecting metal structures between levels. After a final dielectric layer is deposited, a top surface of a metal structure of an uppermost metal layer is exposed through the final dielectric layer to form a front-side electrode, and a bottom surface of a cavity-filled portion of a metal structure of a lowermost metal layer is also exposed through the first dielectric layer to form a back-side electrode.
摘要翻译：一种制造具有导电正面和背面电极或触点的薄膜器件的方法。首先在第一介电层上形成顶侧空腔，然后在第一介电层上沉积金属层以填充空腔。从金属层蚀刻定义的金属结构以包括填充空腔的金属，然后在金属结构上沉积第二介电层。可以以类似的方式形成限定的金属结构的附加水平，其中通孔在层间之间连接金属结构。在沉积最终的介电层之后，通过最终介电层暴露最上层金属层的金属结构的顶表面，形成前侧电极，并且将金属结构的空腔填充部分的底表面最下面的金属层也暴露在第一介电层中以形成背面电极。

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