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1. 发明授权

US08127186B2 Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test 有权
标题翻译：用于估计被测设备的扫描链中的卡入缺陷的位置的方法和装置
公开(公告)号：US08127186B2
公开(公告)日：2012-02-28
申请号：US12074015
申请日：2008-02-28
申请人： Phillip D. Burlison , John K. Frediani
发明人： Phillip D. Burlison , John K. Frediani
IPC分类号： G01R31/3183 , G01R31/40
CPC分类号： G01R31/318566
摘要： As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference has a predetermined relationship to a stored value, the stored value is overwritten using the reference. The stored value is then used to estimate the position of a stuck-at defect in the scan chain.
摘要翻译：当扫描图案从扫描链中移出时，扫描图案被实时评估是否存在逻辑条件。维持对当前正在评估的扫描图案的一部分的引用。当参考与存储值具有预定关系时，在识别出逻辑条件的存在时，使用该参考来重写所存储的值。然后使用存储的值来估计扫描链中卡住缺陷的位置。

2. 发明授权

US07650547B2 Apparatus for locating a defect in a scan chain while testing digital logic 有权
标题翻译：用于在测试数字逻辑时定位扫描链中的缺陷的装置
公开(公告)号：US07650547B2
公开(公告)日：2010-01-19
申请号：US11680134
申请日：2007-02-28
申请人： Phillip D. Burlison , John K. Frediani
发明人： Phillip D. Burlison , John K. Frediani
IPC分类号： G01R31/3183 , G01R31/40
CPC分类号： G01R31/318544 , G01R31/318525
摘要： An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns.
摘要翻译：一种用于通过在包括多个图案的测试期间观察到特定数据状态的串行数据流中记录最后位位置来定位扫描链中的缺陷的装置。

3. 发明授权

US07865788B2 Dynamic mask memory for serial scan testing 有权
标题翻译：用于串行扫描测试的动态屏蔽存储器
公开(公告)号：US07865788B2
公开(公告)日：2011-01-04
申请号：US11941026
申请日：2007-11-15
申请人： Phillip D. Burlison , Mei-Mei Su , John K. Frediani
发明人： Phillip D. Burlison , Mei-Mei Su , John K. Frediani
IPC分类号： G11C29/00
CPC分类号： G01R31/318544
摘要： A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.
摘要翻译：将故障掩模存储器添加到半导体测试器。结合新的故障过滤器，故障可能被忽略或用于更新故障掩码存储器的内容。报告只有第一个失败的实例减少测试数据日志的大小。

4. 发明申请

US20080215940A1 Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test 有权
标题翻译：用于估计被测设备的扫描链中的卡入缺陷的位置的方法和装置
公开(公告)号：US20080215940A1
公开(公告)日：2008-09-04
申请号：US12074015
申请日：2008-02-28
申请人： Phillip D. Burlison , John K. Frediani
发明人： Phillip D. Burlison , John K. Frediani
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318566
摘要： As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference has a predetermined relationship to a stored value, the stored value is overwritten using the reference. The stored value is then used to estimate the position of a stuck-at defect in the scan chain.
摘要翻译：当扫描图案从扫描链中移出时，扫描图案被实时评估是否存在逻辑条件。维持对当前正在评估的扫描图案的一部分的引用。当参考与存储值具有预定关系时，在识别出逻辑条件的存在时，使用该参考来重写所存储的值。然后使用存储的值来估计扫描链中卡住缺陷的位置。

5. 发明授权

US4398246A Word processing system employing a plurality of general purpose processor circuits 失效
标题翻译：采用多个通用处理器电路的字处理系统
公开(公告)号：US4398246A
公开(公告)日：1983-08-09
申请号：US177531
申请日：1980-08-12
申请人： John K. Frediani , Richard E. Johnson , Terrance L. Lillie
发明人： John K. Frediani , Richard E. Johnson , Terrance L. Lillie
IPC分类号： G06F3/153 , G06F13/18 , G06F3/12 , G06F3/04 , G06F3/14
CPC分类号： G06F3/153 , G06F13/18
摘要： A data processing system embodying the present invention includes a plurality of data processing stations. Each station includes a first communications interface connected to a common communication channel and a second communications interface for communicating with one or more associated controlled units. Each station also includes a processor and a memory; the processor and the interfaces being operatively connected to the memory, so that each may access the memory, and to a contention resolving circuit for resolving memory access conflicts. The system also includes a first controlled unit comprising a mass storage device and a controlled unit communications interface connected to the second communications interface of a first one of the plurality of processors; a second controlled unit comprising a keyboard for entering data and a first, single line, display for displaying data and a controlled unit communications interface connected to the second communications interface of a second of the plurality of processors; and a third controlled unit comprising a second, multi-line, display for displaying data and a controlled unit communications interface connected to the second communications interface of a third of a plurality of processors.
摘要翻译：体现本发明的数据处理系统包括多个数据处理站。每个站包括连接到公共通信信道的第一通信接口和用于与一个或多个相关联的受控单元进行通信的第二通信接口。每个站还包括处理器和存储器; 处理器和接口可操作地连接到存储器，使得每个可以访问存储器以及争用解决电路，用于解决存储器访问冲突。该系统还包括第一受控单元，其包括连接到多个处理器中的第一个处理器的第二通信接口的大容量存储设备和受控单元通信接口; 第二受控单元，包括用于输入数据的键盘和用于显示数据的第一单行显示器和连接到所述多个处理器中的第二处理器的第二通信接口的受控单元通信接口; 以及第三受控单元，其包括用于显示数据的第二多行显示器和连接到多个处理器中的三分之一的第二通信接口的受控单元通信接口。

6. 发明授权

US4422070A Circuit for controlling character attributes in a word processing system having a display 失效
标题翻译：用于控制具有显示器的字处理系统中的字符属性的电路
公开(公告)号：US4422070A
公开(公告)日：1983-12-20
申请号：US177651
申请日：1980-08-12
申请人： Robert A. Couper , John K. Frediani , Terrance L. Lillie
发明人： Robert A. Couper , John K. Frediani , Terrance L. Lillie
IPC分类号： G06F3/153 , G09G1/00 , G09G5/30 , G09G1/06
CPC分类号： G09G5/30 , G06F3/153 , G09G1/00
摘要： An attribute control system is provided in a word processing system of the type having a keyboard for entering alpha numeric data. A display control circuit is coupled between a display, which displays a plurality of lines of alpha numeric text, and the keyboard. The display control circuit controls the information exhibited on the display. The display control circuit means includes a character attribute control circuit having a latch for latching attribute signal information entered from the keyboard. The attribute signal information remains in the latch until the attribute latch is cleared or another attribute signal is entered from the keyboard.
摘要翻译：在具有用于输入字母数字数据的键盘的类型的文字处理系统中提供属性控制系统。显示控制电路耦合在显示多个字母数字文本行的显示器和键盘之间。显示控制电路控制显示器上显示的信息。显示控制电路装置包括具有用于锁存从键盘输入的属性信号信息的锁存器的字符属性控制电路。属性信号信息保留在锁存器中，直到属性锁存器被清除或从键盘输入另一个属性信号。

7. 发明授权

US4393377A Circuit for controlling information on a display 失效
标题翻译：用于控制显示器上的信息的电路
公开(公告)号：US4393377A
公开(公告)日：1983-07-12
申请号：US177322
申请日：1980-08-12
申请人： Robert A. Couper , John K. Frediani , Terrance L. Lillie
发明人： Robert A. Couper , John K. Frediani , Terrance L. Lillie
IPC分类号： G09G5/24 , G06F3/153
CPC分类号： G09G5/24
摘要： A circuit for controlling information on a display includes two character generators. Each character generator is coupled to a row counter and a character latch which latches character information. The row counter is energized by line synchronization information. A width generator is coupled to both the character latch and a counter. Two shift registers are connected respectively to the first and second character generators and to a means for generating output signals for application to the display. The counter coupled to the width generator has its output signals applied to the character latch and to the output signal generating means for the display.
摘要翻译：用于控制显示器上的信息的电路包括两个字符发生器。每个字符发生器耦合到行计数器和锁存字符信息的字符锁存器。行计数器由行同步信息激活。宽度发生器耦合到字符锁存器和计数器两者。两个移位寄存器分别连接到第一和第二字符发生器以及用于产生用于应用于显示器的输出信号的装置。耦合到宽度发生器的计数器具有施加到字符锁存器的输出信号和用于显示器的输出信号产生装置。

8. 发明授权

US4387424A Communications systems for a word processing system employing distributed processing circuitry 失效
标题翻译：用于采用分布式处理电路的文字处理系统的通信系统
公开(公告)号：US4387424A
公开(公告)日：1983-06-07
申请号：US177319
申请日：1980-08-12
申请人： John K. Frediani , Terrance L. Lillie
发明人： John K. Frediani , Terrance L. Lillie
IPC分类号： G06F13/18 , G06F13/37 , G06F15/16
CPC分类号： G06F13/18 , G06F13/37
摘要： A communications system includes a plurality of data processing stations each having a first communications means connected to a common communications channel. Each of the data processing stations also includes a second communications means adapted to be connected to one or more associated units. Each station includes a contention resolving circuit connected to a processing means, the first communications means and the second communications means. The contention resolving circuit is further coupled to and controls access to a memory for the data processing station. Controlled units such as mass storage data entry and retrieval means and a keyboard for entering alpha numeric data information, each having a controlled unit communications means are provided. These units are connected by their associated communications means to the second communications means of respective ones of the plurality of data processing stations.
摘要翻译：通信系统包括多个数据处理站，每个数据处理站具有连接到公共通信信道的第一通信装置。每个数据处理站还包括适于连接到一个或多个相关单元的第二通信装置。每个站包括连接到处理装置，第一通信装置和第二通信装置的争用解决电路。争用解决电路还耦合到并控制对数据处理站的存储器的访问。提供诸如大容量存储数据输入和检索装置的控制单元和用于输入字母数字数据信息的键盘，每个具有受控单元通信装置。这些单元通过其相关联的通信装置连接到多个数据处理站中的相应的数据处理站的第二通信装置。

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