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1. 发明授权

US06297089B1 Method of forming buried straps in DRAMs 失效
标题翻译：在DRAM中形成埋地带的方法
公开(公告)号：US06297089B1
公开(公告)日：2001-10-02
申请号：US09447630
申请日：1999-11-23
申请人： Philippe Coronel , Edith Lattard , Renzo Maccagnan
发明人： Philippe Coronel , Edith Lattard , Renzo Maccagnan
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A conventional initial deep trench structure consists of a patterned Si3N4 pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO2 collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO2 is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO2 is etched at least 6 times faster than the Si3N4 (stopping on the Si3N4 pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6× the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages. Next, N-type dopant is implanted in the upper portion of the silicon substrate to create a doped region. The trench is filled with a layer of doped polysilicon (POLY2) which is planarized by chemical-mechanical polishing down to approximately the Si3N4 pad layer surface and finally recessed down to a depth level substantially coplanar with the silicon surface substrate to create a POLY2 stud. The buried strap is formed by the doped region and POLY2 stud. The above method presents significant advantages in terms of product reliability, throughput improvements and process flow simplification.
摘要翻译：常规的初始深沟槽结构由其中形成有深沟槽的经图案化的Si 3 N 4衬垫层包覆的硅衬底组成。沟槽部分地被掺杂多晶硅（POLY1）填充。在所述多晶硅填充物和衬底之间插入电介质膜以形成存储电容器。 TEOS SiO2轴环层共形地涂覆结构的上部。现在，在相同的RIE反应器中进行的两步法中TEOS SiO2被干蚀刻。在第一步中，TEOS SiO2被蚀刻至少比Si3N4快6倍（停止在Si3N4焊盘层上）。在第二步中，操作条件确保部分各向同性的干法蚀刻，优选具有两倍的功率和1.25倍的压力，从而提供6倍的水平速率的垂直蚀刻速率。作为该步骤的结果，沟槽中的硅衬底的上部暴露而不损坏。接下来，将N型掺杂剂注入到硅衬底的上部以产生掺杂区域。沟槽填充有一层掺杂的多晶硅（POLY2），其通过化学机械抛光平坦化到大约Si3N4焊盘层表面，最后凹陷到与硅表面衬底基本上共面的深度级以产生POLY2螺柱。掩埋带由掺杂区域和POLY2螺柱形成。上述方法在产品可靠性，吞吐量改进和工艺流程简化方面具有显着的优势。

2. 发明授权

US06342450B1 Method of forming insulating spacers in DRAM chips 失效
标题翻译：在DRAM芯片中形成绝缘间隔物的方法
公开(公告)号：US06342450B1
公开(公告)日：2002-01-29
申请号：US09607215
申请日：2000-06-30
申请人： Edith Lattard
发明人： Edith Lattard
IPC分类号： H01L21311
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10861
摘要： There is disclosed an improved method of forming the spacer which isolates the gate conductor from the metal contact with the diffusion (source/drain) region of each array transfer transistor for all memory cells of a DRAM chip. According to the method there is provided a structure consisting of a silicon substrate having a diffusion region formed therein and gate conductor (GC) lines formed thereon. Then, an oxynitride layer and a silicon nitride (Si3N4) layer are conformally deposited in sequence onto the structure by LPCVD in the same tool for total clusterization. Next, the structure is anisotropically dry etched with a chemistry that is Si3N4/oxynitride selective to expose the oxynitride layer between the GC lines and the upper portion thereof in a one step process to form the Si3N4 spacers. Still in accordance with the invention, the above method finds a valuable application in the fabrication of borderless metal contacts in DRAM chips wherein the risk of having potential an electrical short between the gate conductor and the metal contact is substantially eliminated.
摘要翻译：公开了一种形成间隔物的改进方法，其将栅极导体与金属接触部分隔离用于DRAM芯片的所有存储单元的每个阵列传输晶体管的扩散（源极/漏极）区域。根据该方法，提供了由形成有扩散区域的硅衬底和形成在其上的栅极导体（GC）线组成的结构。然后，将氧氮化物层和氮化硅（Si 3 N 4）层依次通过LPCVD在相同的工具中共同沉积到结构上以进行总簇化。接下来，通过在一步法中选择性地暴露出GC管线和其上部之间的氮氧化物层的化学物质的结构被各向异性地干蚀刻以形成Si 3 N 4间隔物。仍然根据本发明，上述方法在制造DRAM芯片中的无边界金属触点方面发现了有价值的应用，其中基本上消除了在栅极导体和金属触点之间具有电短路的风险。

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