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1. 发明授权

US5680339A Method for rounding using redundant coded multiply result 失效
标题翻译：使用冗余编码乘法结果舍入的方法
公开(公告)号：US5680339A
公开(公告)日：1997-10-21
申请号：US484625
申请日：1995-06-07
申请人： Philip Moyse , Richard Simpson
发明人： Philip Moyse , Richard Simpson
IPC分类号： G06F7/48 , G06F7/38 , G06F7/00
CPC分类号： G06F7/4824 , G06F7/49947
摘要： A data processing apparatus for rounding an input number coded in a redundant bit form including a magnitude signal and a sign signal for each bit of the input number. A carry path control signal generator (372, 382) forms carry/borrow control signals for each bit of the input number from the corresponding magnitude signal and sign signal. A first borrow ripple unit (386) receives the carry/borrow control signals corresponding to a set of the least significant bits of the input number and a "0" borrow in signal for its least significant and generates a normal coded data signal and a borrow out signal for a most significant bit of this set of least significant bits. A second borrow ripple unit (376) receives the carry/borrow control signals corresponding to the most significant bits and a "1" borrow in signal for its least significant bit and generates a first rounded number having a normal coded data signal. The second rounded number generator includes a mask ripple unit (374) and a bit wise exclusive OR unit (378). A multiplexer (390) selectively outputs as a rounded output number either the first rounded number, the second rounded number or a third normal rounded number equal to one more than the first rounded number. This selection is based upon the normal coded data signal of said most significant bit of the set of least significant bits and the borrow out signal of this bit. In the preferred embodiment of this invention, the rounding unit is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.
摘要翻译：一种数据处理装置，用于舍入以冗余位形式编码的输入数字，包括输入数字的每一位的幅度信号和符号信号。进位路径控制信号发生器（372,382）从对应的幅度信号和符号信号形成输入号码的每一比特的进位/借位控制信号。第一借位波纹单元（386）接收对应于输入号码的最低有效位集合的进位/借位控制信号，并且以最小有效的方式接收信号中的“0”借位，并产生正常编码数据信号和借位输出信号，用于该组最低有效位的最高有效位。第二借位波纹单元（376）接收对应于最高有效位的进位/借位控制信号，并且为其最低有效位接收信号中的“1”借位，并产生具有正常编码数据信号的第一舍入数。第二圆角数字发生器包括掩模纹波单元（374）和位异或异或单元（378）。多路复用器（390）有选择地输出为舍入的输出数字，即第一舍入数，第二舍入数或等于比第一舍入数多一个的第三法向舍入数。该选择基于该比特集合的最高有效位的正常编码数据信号和借位输出信号。在本发明的优选实施例中，舍入单元被实施为至少一个数字图像/图形处理器（71,72,73,74），作为在图像处理中使用的单个集成电路中形成的多处理器（100）的一部分。

2. 发明授权

US5644522A Method, apparatus and system for multiply rounding using redundant coded multiply result 失效
标题翻译：使用冗余编码乘法结果进行乘法舍入的方法，装置和系统
公开(公告)号：US5644522A
公开(公告)日：1997-07-01
申请号：US159650
申请日：1993-11-30
申请人： Philip Moyse , Richard Simpson
发明人： Philip Moyse , Richard Simpson
IPC分类号： G06F7/48 , G06F7/00 , G06F7/38
CPC分类号： G06F7/4824 , G06F7/49947
摘要： A data processing apparatus for rounding an input number coded in a redundant bit form including a magnitude signal and a sign signal for each bit of the input number. A carry path control signal generator (372, 382) forms carry/borrow control signals for each bit of the input number from the corresponding magnitude signal and sign signal. A first borrow ripple unit (386) receives the carry/borrow control signals corresponding to a set of the least significant bits of the input number and a "0" borrow in signal for its least significant and generates a normal coded data signal and a borrow out signal for a most significant bit of this set of least significant bits. A second borrow ripple unit (376) receives the carry/borrow control signals corresponding to the most significant bits and a "1" borrow in signal for its least significant bit and generates a first rounded number having a normal coded data signal. The second rounded number generator includes a mask ripple unit (374) and a bit wise exclusive OR unit (378). A multiplexer (390) selectively outputs as a rounded output number either the first rounded number, the second rounded number or a third normal rounded number equal to one more than the first rounded number. This selection is based upon the normal coded data signal of said most significant bit of the set of least significant bits and the borrow out signal of this bit. In the preferred embodiment of this invention, the rounding unit is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.
摘要翻译：一种数据处理装置，用于舍入以冗余位形式编码的输入数字，包括输入数字的每一位的幅度信号和符号信号。进位路径控制信号发生器（372,382）从对应的幅度信号和符号信号形成输入号码的每一比特的进位/借位控制信号。第一借位波纹单元（386）接收对应于输入号码的最低有效位集合的进位/借位控制信号，并且以最小有效的方式接收信号中的“0”借位，并产生正常编码数据信号和借位输出信号，用于该组最低有效位的最高有效位。第二借位波纹单元（376）接收对应于最高有效位的进位/借位控制信号，并且为其最低有效位接收信号中的“1”借位，并产生具有正常编码数据信号的第一舍入数。第二圆角数字发生器包括掩模纹波单元（374）和位异或异或单元（378）。多路复用器（390）有选择地输出为舍入的输出数字，即第一舍入数，第二舍入数或等于比第一舍入数多一个的第三法向舍入数。该选择基于该比特集合的最高有效位的正常编码数据信号和借位输出信号。在本发明的优选实施例中，舍入单元被实施为至少一个数字图像/图形处理器（71,72,73,74），作为在图像处理中使用的单个集成电路中形成的多处理器（100）的一部分。

3. 发明授权

US5345405A Circuit for detecting the position of an extreme "1" bit in a binary number 失效
标题翻译：用于检测二进制数中极端“1”位的位置的电路
公开(公告)号：US5345405A
公开(公告)日：1994-09-06
申请号：US978005
申请日：1992-11-18
申请人： Brendan Walsh , Richard Simpson , Laura Dudbridge , David Collins , Philip Moyse
发明人： Brendan Walsh , Richard Simpson , Laura Dudbridge , David Collins , Philip Moyse
IPC分类号： G06F7/00 , G06F7/74 , G06F9/305 , H03M7/24
CPC分类号： G06F7/74
摘要： Apparatus for detecting the leftmost "1" bit or the rightmost "1" bit of an input number includes a binary tree (11) of two-inputs OR-gates (13, 14, 15, 16) or their logical equivalent to which the input number is applied in parallel and from which signals are derived and applied as inputs and to control a plurality of trees (MA, MB, MC) of two-input multiplexers (12) from the outputs (E0, E1, E2, E3) of which appear the bits of a number representing the position in the input number of the leftmost "1" or the rightmost "1" bit.
摘要翻译：用于检测输入号码的最左“1”位或最右“1”位的设备包括二输入或门（13,14,15,16）或其逻辑等价物的二叉树（11）输入编号被并行地应用，并从其中导出和施加信号作为输入，并从输出（E0，E1，E2，E3）控制双输入多路复用器（12）的多个树（MA，MB，MC）其中出现代表最左“1”或最右“1”位的输入数位置的数字的位。

4. 发明授权

US09007335B2 Touch-sensing systems 有权
标题翻译：触摸感应系统
公开(公告)号：US09007335B2
公开(公告)日：2015-04-14
申请号：US13520333
申请日：2010-12-21
申请人： Ivan Cronin , Nicholas Simon Terry , Philip Moyse , Edward Simons , Steven Paul Farmer
发明人： Ivan Cronin , Nicholas Simon Terry , Philip Moyse , Edward Simons , Steven Paul Farmer
IPC分类号： G06F3/045 , G06F3/044 , G06F3/041 , G09G3/34
CPC分类号： G06F3/044 , G06F3/0412 , G06F3/0416 , G09G3/344
摘要： A method of projected capacitance touch sensing on a display includes updating the display by applying a drive waveform to each pixel of the display over a plurality of frame periods to update a pixel state. The updating includes selecting each row of the display in turn and repeating a frame update to drive pixels with successive time slices of the drive waveforms. The method further includes sensing a signal from a projected capacitance touch sensing electrode of the display during a sensing interval to provide a touch sensing response; identifying when column drive levels of the drive waveforms for pixels of one selected row change by more than a threshold level between the selected row and a next selected row; and inhibiting the touch sensing responsive to the column drive row change signal indicating a greater than the threshold level change of the drive levels between the selected rows.
摘要翻译：在显示器上的投影电容触摸感测的方法包括通过在多个帧周期上对显示器的每个像素施加驱动波形来更新显示，以更新像素状态。更新包括依次选择显示器的每一行并重复帧更新以驱动具有驱动波形的连续时间片的像素。该方法还包括在感测间隔期间感测来自显示器的投影电容触摸感测电极的信号以提供触摸感测响应; 识别一个所选行的像素的驱动波形的列驱动电平何时在所选择的行和下一个所选行之间改变多于阈值电平; 以及响应于列驱动行改变信号来禁止触摸感测，该信号指示大于所选行之间的驱动电平的阈值电平变化。

5. 发明授权

US09007298B2 Display control mode 有权
标题翻译：显示控制模式
公开(公告)号：US09007298B2
公开(公告)日：2015-04-14
申请号：US13816926
申请日：2011-08-12
申请人： Philip Moyse
发明人： Philip Moyse
IPC分类号： G02F1/167 , G09G3/02 , G09G3/20 , G09G3/34
CPC分类号： G09G3/02 , G09G3/2025 , G09G3/3433 , G09G2300/023 , G09G2310/0205 , G09G2310/0216 , G09G2310/0218 , G09G2310/0221 , G09G2310/0224 , G09G2310/0227 , G09G2320/0257
摘要： A method updates an image displayed on an electronic display. The image can include a first region having multiple lines and a second region also having multiple lines. The method includes driving the pixels of the first and second regions according to one or more frames. In a first frame, driving the pixels of the first and second regions is done by scanning the lines of the regions from a first end of the first region to a second end of the second region, the second end opposite the first end along a scanning direction. In a second frame, driving the pixels of the first and second regions is done by scanning the lines of the regions from the first end to the second end, and the scanning begins before the scanning according to the first frame reaches the second end.
摘要翻译：方法更新显示在电子显示器上的图像。图像可以包括具有多条线的第一区域和也具有多条线路的第二区域。该方法包括根据一个或多个帧来驱动第一和第二区域的像素。在第一帧中，通过将区域的线从第一区域的第一端扫描到第二区域的第二端来完成驱动第一和第二区域的像素，第二端沿着扫描方向。在第二帧中，驱动第一和第二区域的像素是通过扫描从第一端到第二端的区域的线来完成的，并且扫描在根据第一帧的扫描之前开始到达第二端。

6. 发明申请

US20130201146A1 TOUCH-SENSING SYSTEMS 有权
标题翻译：触摸感应系统
公开(公告)号：US20130201146A1
公开(公告)日：2013-08-08
申请号：US13520333
申请日：2010-12-21
申请人： Ivan Cronin , Nicholas Simon Terry , Philip Moyse , Edward Simons , Steven Paul Farmer
发明人： Ivan Cronin , Nicholas Simon Terry , Philip Moyse , Edward Simons , Steven Paul Farmer
IPC分类号： G06F3/044
CPC分类号： G06F3/044 , G06F3/0412 , G06F3/0416 , G09G3/344
摘要： A method of projected capacitance touch sensing on a display screen, the method comprising: updating said display screen by applying a drive waveform to each pixel of the display screen over a plurality of frame periods, wherein a said drive waveform for a pixel defines a transition of the pixel from a current pixel state to an updated pixel state over said plurality of frame periods, and wherein said updating comprises selecting each row of said display screen in turn for a row driving period and driving columns of the display screen with a time slice of drive waveforms for pixels of the row to perform a frame update of said display screen, and repeating said frame update to drive pixels of said display with a plurality of successive time slices of said drive waveforms to drive said pixels with said drive waveforms; sensing a signal from a projected capacitance touch sensing electrode of said display screen during a sensing interval, and using said sensing to provide a touch sensing response; identifying when column drive levels of said drive waveforms for pixels of one selected row change by more than a threshold level between said one selected row and a next selected row to provide a column drive row change signal; and inhibiting said touch sensing responsive to said column drive row change signal indicating a greater than said threshold level change of said column drive levels from said one selected row to said next selected row during said sensing interval.
摘要翻译：一种在显示屏幕上投射电容触摸感测的方法，所述方法包括：通过在多个帧周期向所述显示屏幕的每个像素施加驱动波形来更新所述显示屏幕，其中所述用于像素的所述驱动波形限定转换在所述多个帧周期中从当前像素状态到更新像素状态的像素，并且其中所述更新包括依次选择行驱动周期的所述显示屏的每行，并且以时间片驱动显示屏的列的所述行的像素的驱动波形，以执行所述显示屏的帧更新，并且重复所述帧更新以用所述驱动波形的多个连续时间片驱动所述显示的像素，以用所述驱动波形驱动所述像素; 在感测间隔期间感测来自所述显示屏幕的投影电容触摸感应电极的信号，并且使用所述感测来提供触摸感测响应; 识别所述一个选定行的像素的所述驱动波形的列驱动电平何时在所述一个所选行和下一个所选行之间改变多于阈值电平以提供列驱动行改变信号; 以及响应于所述列驱动行改变信号禁止所述触摸感测，所述列驱动行改变信号指示在所述感测间隔期间所述列驱动电平从所述一个所选行到所述下一个所选行的所述阈值电平变化大于所述阈值电平。

7. 发明授权

US5734880A Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections 失效
标题翻译：硬件分支采用根据划分成多个部分的算术逻辑单元的部分的状态加载的循环控制寄存器
公开(公告)号：US5734880A
公开(公告)日：1998-03-31
申请号：US480230
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F15/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation. An arithmetic logic unit operation generates a status bit loaded into a status register or is split into sections and generates a status bit for each section stored in a multiple flags register (211) used to load the loop. count register. If this is zero then the loop priority logic reloads the program counter (701) with the loop start address and repeats the loop. If this is nonzero, program counter (701) may increment normally or will be loaded with the loop start address of a higher priority loop.
摘要翻译：条件硬件分支采用零开销循环逻辑并写入程序循环内的循环计数寄存器。零开销循环逻辑包括程序计数器（701），循环结束寄存器（711,712,713），循环开始寄存器（721,722,723），循环计数器寄存器（731,732,733），比较器（715， 716,717）和循环优先级逻辑（725）。通常，每个周期递增程序计数器（701）。比较器（715,716,717）将存储在程序计数器（701）中的地址与相应的循环结束寄存器（711,712,713）进行比较。如果程序计数器（701）中的地址等于循环结束地址，则循环优先级逻辑（725）递减循环计数寄存器，并加载循环起始寄存器中循环起始地址的程序计数器。硬件循环涉及在程序循环操作期间加载循环计数寄存器。算术逻辑单元操作产生加载到状态寄存器中的状态位或分割成部分，并且生成用于加载循环的多标志寄存器（211）中存储的每个部分的状态位。计数寄存器如果这是零，则循环优先级逻辑使用循环起始地址重新加载程序计数器（701）并重复循环。如果这是非零的，则程序计数器（701）可以正常地增加或将加载较高优先级循环的循环起始地址。

8. 发明申请

US20070041224A1 Switch mode power supply control systems 失效
标题翻译：开关电源控制系统
公开(公告)号：US20070041224A1
公开(公告)日：2007-02-22
申请号：US11481485
申请日：2006-07-06
申请人： Philip Moyse , David Coulson , Russell Jacques , David Garner
发明人： Philip Moyse , David Coulson , Russell Jacques , David Garner
IPC分类号： H02M3/335 , G05F1/00
CPC分类号： H02M3/157 , H02M3/33507 , H02M3/33515 , H02M2001/0032 , Y02B70/16
摘要： We describe a switch mode power supply (SMPS) controller employing a combination of pulse frequency and pulse width modulation. The controller employs a “gear box” control scheme using two complementary control loops, one for real-time control of the SMPS using PFM and a second using a PWM control scheme which monitors the switching frequency and, at defined operating points, adjusts the pulse width up or down through a set of pre-determined values. This can be considered analogous to the gearbox of a motor vehicle with the SMPS pulse width, switching frequency and output power roughly corresponding to the vehicle's gear ratio, engine speed and road speed respectively.
摘要翻译：我们描述采用脉冲频率和脉冲宽度调制的组合的开关电源（SMPS）控制器。控制器采用“齿轮箱”控制方案，使用两个互补控制回路，一个用于使用PFM对SMPS进行实时控制;另一个使用PWM控制方案来监控开关频率，并且在规定的工作点调整脉冲通过一组预先确定的值向上或向下宽。这可以被认为类似于具有SMPS脉冲宽度，开关频率和输出功率的机动车辆的齿轮箱，其大致对应于车辆的传动比，发动机转速和道路速度。

9. 发明授权

US5761726A Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效
标题翻译：在具有与每个处理器对应的统一地址空间的多个存储器的多处理系统中产生基地址
公开(公告)号：US5761726A
公开(公告)日：1998-06-02
申请号：US479981
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F12/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.
摘要翻译：多处理系统包括多个存储器和多个处理器。每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。每个处理器具有预定的多个对应的存储器。这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。在任一个处理器上执行的基地址指令产生与该处理器对应的基地址。基址优选地代替包括一组基地址寄存器，一组索引地址寄存器和全加器的地址单元中的基地址寄存器的内容。

10. 发明授权

US5634065A Three input arithmetic logic unit with controllable shifter and mask generator 失效
标题翻译：三输入算术逻辑单元，带可控制移位器和掩码发生器
公开(公告)号：US5634065A
公开(公告)日：1997-05-27
申请号：US475134
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F7/575 , G06F7/76 , G06F7/38
CPC分类号： G06F7/764 , G06F5/01 , G06F7/575
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

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