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1. 发明申请

US20120048596A1 Structure And Process For Electrical Interconnect And Thermal Management 有权
标题翻译：电气互连和热管理的结构和过程
公开(公告)号：US20120048596A1
公开(公告)日：2012-03-01
申请号：US13238975
申请日：2011-09-21
申请人： Philip GARROU , Charles Kenneth Williams , Christopher A. Bower
发明人： Philip GARROU , Charles Kenneth Williams , Christopher A. Bower
IPC分类号： H05K7/20 , H01L21/762
CPC分类号： H01L23/473 , H01L23/481 , H01L25/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/05 , H01L2224/05548 , H01L2224/13 , H01L2224/13024 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06589 , H01L2924/09701 , H01L2924/13091 , H01L2924/014 , H01L2924/00
摘要： A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.
摘要翻译：一种用于制造电路装置的热管理结构的方法。该方法提供第一基板和第二基板，其中第一和第二基板中的至少一个包括电路元件。所述方法在所述第一基板和所述第二基板中的至少一个中形成延伸穿过所述第一基板或所述第二基板的厚度的入口通孔，在所述第一基板和所述第二基板的至少一个中形成出口通孔，延伸通过第一基板或第二基板的厚度的孔，在第一和第二基板中的至少一个上形成相应的结合元件，并且在相应的接合元件处将第一和第二基板结合以形成第一和第二基板之间的密封并且在第一和第二基板之间形成第一冷却剂通道。

2. 发明授权

US08486765B2 Structure and process for electrical interconnect and thermal management 有权
标题翻译：电气互连和热管理的结构和过程
公开(公告)号：US08486765B2
公开(公告)日：2013-07-16
申请号：US13238975
申请日：2011-09-21
申请人： Philip Garrou , Charles Kenneth Williams , Christopher A. Bower
发明人： Philip Garrou , Charles Kenneth Williams , Christopher A. Bower
IPC分类号： H01L21/00
CPC分类号： H01L23/473 , H01L23/481 , H01L25/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/05 , H01L2224/05548 , H01L2224/13 , H01L2224/13024 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06589 , H01L2924/09701 , H01L2924/13091 , H01L2924/014 , H01L2924/00
摘要： A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.
摘要翻译：一种用于制造电路装置的热管理结构的方法。该方法提供第一基板和第二基板，其中第一和第二基板中的至少一个包括电路元件。所述方法在所述第一基板和所述第二基板中的至少一个中形成延伸穿过所述第一基板或所述第二基板的厚度的入口通孔，在所述第一基板和所述第二基板的至少一个中形成出口通孔，延伸通过第一基板或第二基板的厚度的孔，在第一和第二基板中的至少一个上形成相应的结合元件，并且在相应的接合元件处将第一和第二基板结合以形成第一和第二基板之间的密封并且在第一和第二基板之间形成第一冷却剂通道。

3. 发明授权

US08035223B2 Structure and process for electrical interconnect and thermal management 有权
标题翻译：电气互连和热管理的结构和过程
公开(公告)号：US08035223B2
公开(公告)日：2011-10-11
申请号：US11846253
申请日：2007-08-28
申请人： Philip Garrou , Charles Kenneth Williams , Christopher A. Bower
发明人： Philip Garrou , Charles Kenneth Williams , Christopher A. Bower
IPC分类号： H01L23/34
CPC分类号： H01L23/473 , H01L23/481 , H01L25/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/05 , H01L2224/05548 , H01L2224/13 , H01L2224/13024 , H01L2224/13025 , H01L2224/131 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06589 , H01L2924/09701 , H01L2924/13091 , H01L2924/014 , H01L2924/00
摘要： A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element. The method supplies a fluid through the entrance through-hole, flows the fluid through the coolant channel between the first substrate and second substrates, and removes the fluid from the coolant channel through the exit through-hole.
摘要翻译：集成电路热管理的结构和方法。集成电路的热管理结构包括接合在一起的第一和第二基板，第一和第二基板中的至少一个包括至少一个电路元件，入口通孔的长度延伸穿过至少一个的厚度第一基板和第二基板，具有延伸穿过第一基板和第二基板中的至少一个的厚度的长度的出口通孔，在第一和第二基板之间形成密封件的接合元件，第一和第二基板以及形成在第一和第二基板之间的空间中的冷却剂通道，使得进入入口通孔的流体穿过冷却剂通道和出口通孔以向电路元件提供冷却。该方法通过入口通孔提供流体，使流体流过第一基板和第二基板之间的冷却剂通道，并通过出口通孔从冷却剂通道中除去流体。

4. 发明授权

US08975753B2 Three dimensional interconnect structure and method thereof 有权
标题翻译：三维互连结构及其方法
公开(公告)号：US08975753B2
公开(公告)日：2015-03-10
申请号：US13202187
申请日：2010-03-03
申请人： Charles Kenneth Williams , Christopher A. Bower , Dean Michael Malta , Dorota Temple
发明人： Charles Kenneth Williams , Christopher A. Bower , Dean Michael Malta , Dorota Temple
IPC分类号： H01L23/52 , H01L23/48 , H01L21/768 , H01L25/065 , H01L25/00
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/45147 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/00 , H01L2224/48 , H01L2924/01033
摘要： A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.
摘要翻译：三维互连包括结合到第二衬底的第一衬底，第一衬底包括器件层和体半导体层，设置在第二衬底上的金属焊盘，设置在第一和第二衬底之间的电绝缘层。该结构具有穿过器件层，体半导体层和电绝缘层延伸到第二衬底上的金属焊盘的通孔。该结构在通孔的侧壁上具有介电涂层，以及设置在第二基板上的金属焊盘的等离子体处理区域。该结构包括从金属焊盘的等离子体处理区域通过通孔一体地延伸的通孔金属，并将第一基板的器件层与第二基板的金属焊盘电连接。

5. 发明申请

US20110298134A1 THREE DIMENSIONAL INTERCONNECT STRUCTURE AND METHOD THEREOF 有权
标题翻译：三维互连结构及其方法
公开(公告)号：US20110298134A1
公开(公告)日：2011-12-08
申请号：US13202187
申请日：2010-03-03
申请人： Charles Kenneth Williams , Christopher A. Bower , Dean Michael Malta , Dorota Temple
发明人： Charles Kenneth Williams , Christopher A. Bower , Dean Michael Malta , Dorota Temple
IPC分类号： H01L23/48 , H01L21/60 , H01L23/522 , B23K1/20 , H01L23/532
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/45147 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/00 , H01L2224/48 , H01L2924/01033
摘要： A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semi-conductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.
摘要翻译：三维互连包括结合到第二衬底的第一衬底，第一衬底包括器件层和体半导体层，设置在第二衬底上的金属焊盘，设置在第一和第二衬底之间的电绝缘层。该结构具有穿过器件层延伸的通孔，体半导体层和电绝缘层到第二衬底上的金属焊盘。该结构在通孔的侧壁上具有介电涂层，以及设置在第二基板上的金属焊盘的等离子体处理区域。该结构包括从金属焊盘的等离子体处理区域通过通孔一体地延伸的通孔金属，并将第一基板的器件层与第二基板的金属焊盘电连接。

6. 发明申请

US20110017703A1 SELECTIVE PLANARIZATION METHOD AND DEVICES FABRICATED ON PLANARIZED STRUCTURES 审中-公开
标题翻译：选择性平面化方法和在平面结构上制作的器件
公开(公告)号：US20110017703A1
公开(公告)日：2011-01-27
申请号：US12921482
申请日：2009-02-13
申请人： Dorota Temple , Dean Michael Malta , Christopher A. Bower
发明人： Dorota Temple , Dean Michael Malta , Christopher A. Bower
IPC分类号： H05K3/00 , C23F1/04
CPC分类号： H01L21/32115 , H01L21/32134 , H01L21/7684 , H01L21/76898
摘要： A method and system for treating a surface structure of a workpiece. The method provides a carrier-gel to the surface structure of the workpiece. The carrier-gel includes an etchant for selectively etching a first material of the surface structure and has a gel particle size larger than the surface structure. The method etches the first material from the surface structure by a reaction of the etchant included in the carrier-gel with the first material of the surface structure in order to remove a part of the first material from the surface structure for subsequent device fabrication. The system includes a chemical reactor supporting the workpiece. The chemical reactor is configured to flow the carrier-gel noted to the surface structure of the workpiece in order to remove the first material from the surface structure.
摘要翻译：一种用于处理工件的表面结构的方法和系统。该方法为工件的表面结构提供载体凝胶。载体凝胶包括用于选择性蚀刻表面结构的第一材料并具有大于表面结构的凝胶粒径的蚀刻剂。该方法通过包含在载体 - 凝胶中的蚀刻剂与表面结构的第一材料的反应从表面结构中蚀刻第一材料，以便从表面结构中去除一部分第一材料以用于随后的器件制造。该系统包括一个支撑工件的化学反应器。化学反应器被配置成流动与工件的表面结构相关的载体凝胶，以从表面结构去除第一材料。

7. 发明申请

US20110031388A1 FARADAY CUP ARRAY INTEGRATED WITH A READOUT IC AND METHOD FOR MANUFACTURE THEREOF 有权
标题翻译：集成了读出IC的阵列阵列及其制造方法
公开(公告)号：US20110031388A1
公开(公告)日：2011-02-10
申请号：US12921508
申请日：2009-02-27
申请人： Christopher A. Bower , Kristin Hedgepath Gilchrist , Brian R. Stoner , Dorota Temple
发明人： Christopher A. Bower , Kristin Hedgepath Gilchrist , Brian R. Stoner , Dorota Temple
IPC分类号： H01J49/26 , G01N23/00 , G01T1/00 , B01D59/44 , H01J27/02 , H05K13/00 , B82Y99/00
CPC分类号： H01J49/025 , H01J37/244 , H01J49/0018 , H01J2237/24405 , Y10T29/49002
摘要： A detector array and method for making the detector array. The array includes a substrate including a plurality of trenches formed therein, and includes a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charge particles incident on respective ones of the collectors and to output from said collectors signals indicative of charged particle collection. The array includes a plurality of readout circuits disposed on a side of the substrate opposite openings to the collectors. The readout circuits are configured to read charge collection signals from respective ones of the plurality of collectors.
摘要翻译：用于制造检测器阵列的检测器阵列和方法。该阵列包括一个衬底，该衬底包括形成在其中的多个沟槽，并且包括彼此电隔离的多个集电极，形成在沟槽的壁上，并且被配置成收集入射在相应集电极上的电荷粒子，并从所述收集器信号指示带电粒子收集。该阵列包括多个读出电路，该读出电路设置在基板的与集电体相对的开口的一侧。读出电路被配置为从多个收集器中的相应的一个收集器读取电荷收集信号。

8. 发明申请

US20110006204A1 HIGH DENSITY FARADAY CUP ARRAY OR OTHER OPEN TRENCH STRUCTURES AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：高密度法兰杯阵列或其他开放式结构及其制造方法
公开(公告)号：US20110006204A1
公开(公告)日：2011-01-13
申请号：US12921525
申请日：2009-02-24
申请人： Christopher A. Bower , Kristin Hedgepath Gilchrist , Brian R. Stoner
发明人： Christopher A. Bower , Kristin Hedgepath Gilchrist , Brian R. Stoner
IPC分类号： H01J99/00 , G01T1/00 , H01J49/26 , H01J27/20 , H01J27/02 , H01J37/28 , H01J37/26 , B01D59/44 , H01L31/18
CPC分类号： H01J49/025
摘要： A detector array and method for making the detector array. The detector array includes a substrate including a plurality of trenches formed therein, and a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charged particles incident on respective ones of the collectors and to output from the collectors signals indicative of charged particle collection. In the detector array, adjacent ones of the plurality of trenches are disposed in a staggered configuration relative to one another. The method forms in a substrate a plurality of trenches across a surface of the substrate such that adjacent ones of the trenches are in a staggered sequence relative to one another, forms in the plurality of trenches a plurality of collectors, and connects a plurality of electrodes respectively to the collectors.
摘要翻译：用于制造检测器阵列的检测器阵列和方法。探测器阵列包括一个衬底，该衬底包括形成在其中的多个沟槽，以及形成在沟槽壁上的彼此电隔离的多个集电极，并且被配置成收集入射在相应集电极上的带电粒子，并从收集器信号指示带电粒子收集。在检测器阵列中，多个沟槽中的相邻的沟槽相对于彼此以交错的配置布置。该方法在衬底中形成穿过衬底的表面的多个沟槽，使得相邻的沟槽相对于彼此处于交错的序列，在多个沟槽中形成多个集电极，并且连接多个电极分别给收藏家。

9. 发明授权

US08866081B2 High density faraday cup array or other open trench structures and method of manufacture thereof 有权
标题翻译：高密度法拉第杯阵列或其他开槽结构及其制造方法
公开(公告)号：US08866081B2
公开(公告)日：2014-10-21
申请号：US12921525
申请日：2009-02-24
申请人： Christopher A. Bower , Kristin Hedgepath Gilchrist , Brian R. Stoner
发明人： Christopher A. Bower , Kristin Hedgepath Gilchrist , Brian R. Stoner
IPC分类号： G01T1/00 , H01J49/02
CPC分类号： H01J49/025
摘要： A detector array and method for making the detector array. The detector array includes a substrate including a plurality of trenches formed therein, and a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charged particles incident on respective ones of the collectors and to output from the collectors signals indicative of charged particle collection. In the detector array, adjacent ones of the plurality of trenches are disposed in a staggered configuration relative to one another. The method forms in a substrate a plurality of trenches across a surface of the substrate such that adjacent ones of the trenches are in a staggered sequence relative to one another, forms in the plurality of trenches a plurality of collectors, and connects a plurality of electrodes respectively to the collectors.
摘要翻译：用于制造检测器阵列的检测器阵列和方法。探测器阵列包括一个衬底，该衬底包括形成在其中的多个沟槽，以及形成在沟槽壁上的彼此电隔离的多个集电极，并且被配置成收集入射在相应集电极上的带电粒子，并从收集器信号指示带电粒子收集。在检测器阵列中，多个沟槽中的相邻的沟槽相对于彼此以交错的配置布置。该方法在衬底中形成穿过衬底的表面的多个沟槽，使得相邻的沟槽相对于彼此处于交错的序列，在多个沟槽中形成多个集电极，并且连接多个电极分别给收藏家。

10. 发明授权

US08866080B2 Faraday cup array integrated with a readout IC and method for manufacture thereof 有权
标题翻译：与读出IC集成的法拉第杯阵列及其制造方法
公开(公告)号：US08866080B2
公开(公告)日：2014-10-21
申请号：US12921508
申请日：2009-02-27
申请人： Christopher A. Bower , Kristin Hedgepath Gilchrist , Brian R. Stoner , Dorota Temple
发明人： Christopher A. Bower , Kristin Hedgepath Gilchrist , Brian R. Stoner , Dorota Temple
IPC分类号： G01N23/00 , H01J37/244 , H01J49/02 , H01J49/00
CPC分类号： H01J49/025 , H01J37/244 , H01J49/0018 , H01J2237/24405 , Y10T29/49002
摘要： A detector array and method for making the detector array. The array includes a substrate including a plurality of trenches formed therein, and includes a plurality of collectors electrically isolated from each other, formed on the walls of the trenches, and configured to collect charge particles incident on respective ones of the collectors and to output from said collectors signals indicative of charged particle collection. The array includes a plurality of readout circuits disposed on a side of the substrate opposite openings to the collectors. The readout circuits are configured to read charge collection signals from respective ones of the plurality of collectors.
摘要翻译：用于制造检测器阵列的检测器阵列和方法。该阵列包括一个衬底，该衬底包括形成在其中的多个沟槽，并且包括彼此电隔离的多个集电极，形成在沟槽的壁上，并且被配置成收集入射在相应集电极上的电荷粒子，并从所述收集器信号指示带电粒子收集。该阵列包括多个读出电路，该读出电路设置在基板的与集电体相对的开口的一侧。读出电路被配置为从多个收集器中的相应的一个收集器读取电荷收集信号。

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