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1. 发明授权

US09324730B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09324730B2
公开(公告)日：2016-04-26
申请号：US14601496
申请日：2015-01-21
申请人： Phil-Ouk Nam , Dong-Chul Yoo , Bi-O Kim , Jae-Young Ahn , Byong-Hyun Jang , Ki-Hyun Hwang
发明人： Phil-Ouk Nam , Dong-Chul Yoo , Bi-O Kim , Jae-Young Ahn , Byong-Hyun Jang , Ki-Hyun Hwang
IPC分类号： H01L29/792 , H01L27/115 , H01L27/02
CPC分类号： H01L27/11582 , H01L27/0207 , H01L27/11565 , H01L27/1157
摘要： A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.
摘要翻译：一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

2. 发明申请

US20150145021A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20150145021A1
公开(公告)日：2015-05-28
申请号：US14517025
申请日：2014-10-17
申请人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
发明人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
IPC分类号： H01L27/115 , H01L29/51
CPC分类号： H01L27/11565 , H01L27/1158 , H01L29/66833 , H01L29/7926
摘要： Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.
摘要翻译：非易失性存储器件包括至少四个圆柱形沟道区域，当从垂直于衬底表面的垂直方向观察时，至少四个圆柱形沟道区域从位于至少一个菱形晶体的相应顶点处的衬底的部分垂直延伸。电荷存储层（例如，ONO层）设置在每个圆柱形沟道区的外侧壁上。此外，为了实现高度的集成，提供了多个垂直堆叠的栅电极，其在每个圆柱形沟道区域附近延伸。

3. 发明授权

US09431414B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09431414B2
公开(公告)日：2016-08-30
申请号：US14517025
申请日：2014-10-17
申请人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
发明人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11565 , H01L27/1158 , H01L29/66833 , H01L29/7926
摘要： Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.
摘要翻译：非易失性存储器件包括至少四个圆柱形沟道区域，当从垂直于衬底表面的垂直方向观察时，至少四个圆柱形沟道区域从位于至少一个菱形晶体的相应顶点处的衬底的部分垂直延伸。电荷存储层（例如，ONO层）设置在每个圆柱形沟道区的外侧壁上。此外，为了实现高度的集成，提供了多个垂直堆叠的栅电极，其在每个圆柱形沟道区域附近延伸。

4. 发明授权

US09082659B1 Methods of forming vertical type semiconductor devices including oxidation target layers 有权
标题翻译：形成包括氧化靶层的垂直型半导体器件的方法
公开(公告)号：US09082659B1
公开(公告)日：2015-07-14
申请号：US14643527
申请日：2015-03-10
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7889 , H01L29/7926
摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.
摘要翻译：垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于第一垂直间隙。水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

5. 发明申请

US20150187790A1 METHODS OF FORMING VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS 审中-公开
标题翻译：形成包含氧化目标层的垂直型半导体器件的方法
公开(公告)号：US20150187790A1
公开(公告)日：2015-07-02
申请号：US14643527
申请日：2015-03-10
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7889 , H01L29/7926
摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.
摘要翻译：垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙比第二垂直间隙宽第一垂直间隙。水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

6. 发明授权

US08987805B2 Vertical type semiconductor devices including oxidation target layers 有权
标题翻译：包括氧化靶层的垂直型半导体器件
公开(公告)号：US08987805B2
公开(公告)日：2015-03-24
申请号：US13971347
申请日：2013-08-20
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L29/792 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7889 , H01L29/7926
摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.
摘要翻译：垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于第一垂直间隙。水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

7. 发明申请

US20140054676A1 VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS 有权
标题翻译：垂直型半导体器件，包括氧化目标层
公开(公告)号：US20140054676A1
公开(公告)日：2014-02-27
申请号：US13971347
申请日：2013-08-20
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7889 , H01L29/7926
摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.
摘要翻译：垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于第一垂直间隙。水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

8. 发明申请

US20120276696A1 VERTICAL STRUCTURE NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：垂直结构非易失性存储器件及其制造方法
公开(公告)号：US20120276696A1
公开(公告)日：2012-11-01
申请号：US13456415
申请日：2012-04-26
申请人： Jun-Kyu Yang , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn , Han-Mei Choi , Dong-Chul Yoo
发明人： Jun-Kyu Yang , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn , Han-Mei Choi , Dong-Chul Yoo
IPC分类号： H01L21/336
CPC分类号： H01L29/7926 , H01L27/11556 , H01L27/11582 , H01L29/7889
摘要： A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.
摘要翻译：一种垂直结构的非易失性存储器件，其中防止栅介质层向衬底突出; 降低了接地选择线（GSL）电极的电阻，使得非易失性存储器件高度集成并且具有改进的可靠性，并且提供了其制造方法。该方法包括：在硅衬底上依次形成多晶硅层和绝缘层; 通过所述多晶硅层和所述绝缘层形成栅介质层和沟道层，所述栅介质层和所述沟道层在垂直于所述硅衬底的方向上延伸; 形成用于使所述硅衬底暴露于所述绝缘层和所述多晶硅层的开口; 通过在预定温度下使用含卤素反应气体去除通过开口暴露的多晶硅层; 并在通过去除多晶硅层形成的空间中填充金属层。

9. 发明授权

US09461061B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09461061B2
公开(公告)日：2016-10-04
申请号：US14546172
申请日：2014-11-18
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Jin-Gyun Kim , Jae-Young Ahn , Hun Hyeong Lim , Ki-Hyun Hwang
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Jin-Gyun Kim , Jae-Young Ahn , Hun Hyeong Lim , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.
摘要翻译：制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道，蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

10. 发明授权

US09064895B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09064895B2
公开(公告)日：2015-06-23
申请号：US13943911
申请日：2013-07-17
申请人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/66 , H01L21/8239 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66666 , H01L21/8239 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.
摘要翻译：提供制造垂直存储器件的方法包括在衬底上形成多个交替绝缘层和牺牲层; 图案化和蚀刻所述多个绝缘层和牺牲层以限定暴露所述衬底的表面的至少一部分的开口; 在开口的侧壁上形成电荷捕获图案和隧道绝缘图案; 在开口的侧壁上的隧道绝缘层上形成沟道层，沟道层包括N型杂质掺杂多晶硅; 在开口中的沟道层上形成掩埋绝缘图案; 以及在沟道层的一个侧壁的电荷捕获图案上形成阻挡电介质层和控制栅极。

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