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1. 发明申请

US20110231640A1 METHODS AND APPARATUS FOR PRIORITY INITIALIZATION OF A SECOND PROCESSOR 有权
标题翻译：第二处理器优先初始化的方法和装置
公开(公告)号：US20110231640A1
公开(公告)日：2011-09-22
申请号：US12887196
申请日：2010-09-21
申请人： Phani B. Avadhanam
发明人： Phani B. Avadhanam
IPC分类号： G06F9/24
CPC分类号： G06F9/4403 , G06F9/4405
摘要： Methods and systems provide for activating a second processor by a first processor in a dual processor device early within an initialization routine to enable the second processor to help complete initialization operations. The first processor may prepare a second processor chip for start up, configure the second chip's pins, program the second processor, download a firmware image on the second processor, and initiate operations on the second processor. By performing this initialization early within the initialization routine, the second processor can assist in the initialization routine.
摘要翻译：方法和系统提供了在初始化程序中早期的双处理器设备中的第一处理器激活第二处理器，以使得第二处理器能够帮助完成初始化操作。第一处理器可以准备用于启动的第二处理器芯片，配置第二芯片的引脚，对第二处理器进行编程，在第二处理器上下载固件图像，以及在第二处理器上启动操作。通过在初始化程序中提早执行该初始化，第二处理器可以辅助初始化程序。

2. 发明授权

US08938609B2 Methods and apparatus for priority initialization of a second processor 有权
标题翻译：用于第二处理器的优先初始化的方法和装置
公开(公告)号：US08938609B2
公开(公告)日：2015-01-20
申请号：US12887196
申请日：2010-09-21
申请人： Phani B. Avadhanam
发明人： Phani B. Avadhanam
IPC分类号： G06F9/00 , G06F15/177 , G06F9/44
CPC分类号： G06F9/4403 , G06F9/4405
摘要： Methods and systems provide for activating a second processor by a first processor in a dual processor device early within an initialization routine to enable the second processor to help complete initialization operations. The first processor may prepare a second processor chip for start up, configure the second chip's pins, program the second processor, download a firmware image on the second processor, and initiate operations on the second processor. By performing this initialization early within the initialization routine, the second processor can assist in the initialization routine.
摘要翻译：方法和系统提供了在初始化程序中早期的双处理器设备中的第一处理器激活第二处理器，以使得第二处理器能够帮助完成初始化操作。第一处理器可以准备用于启动的第二处理器芯片，配置第二芯片的引脚，对第二处理器进行编程，在第二处理器上下载固件图像，以及在第二处理器上启动操作。通过在初始化程序中提早执行该初始化，第二处理器可以辅助初始化程序。

3. 发明授权

US08639852B2 Burst access protocol 有权
标题翻译：突发访问协议
公开(公告)号：US08639852B2
公开(公告)日：2014-01-28
申请号：US12887206
申请日：2010-09-21
申请人： Ramkumar Sampathkumar , Phani B. Avadhanam , Siddharth Jayaraman , Michael Bailey
发明人： Ramkumar Sampathkumar , Phani B. Avadhanam , Siddharth Jayaraman , Michael Bailey
IPC分类号： G06F3/00
CPC分类号： G06F9/4403 , G06F9/4405
摘要： Methods and systems provide a burst access protocol that enables efficient transfer of data between a first and a second processor via a data interface whose access set up time could present a communication bottleneck. Data, indices, and/or instructions are transmitted in a static table from the first processor and stored in memory accessible to the second processor. Later, the first processor transmit to the second processor a dynamic table which specifies particular data, indices and/or instructions within the static table that are to be implemented by the second processor. The second processor uses the dynamic table to implement the identified particular subset of data, indices and/or instructions. By transmitting the bulk of data, indices and/or instructions to the second processor in a large static table, the burst access protocol enables efficient use of data interfaces which can transmit large amounts of information, but require relatively long access setup times.
摘要翻译：方法和系统提供突发接入协议，其能够经由其接入建立时间可能呈现通信瓶颈的数据接口在第一和第二处理器之间有效地传送数据。数据，索引和/或指令在静态表中从第一处理器发送并存储在第二处理器可访问的存储器中。之后，第一处理器向第二处理器发送动态表，该动态表指定要由第二处理器实现的静态表内的特定数据，索引和/或指令。第二处理器使用动态表来实现所识别的数据，索引和/或指令的特定子集。通过将大量数据，索引和/或指令发送到大型静态表中的第二处理器，突发存取协议能够有效利用可传输大量信息但需要相对长的访问建立时间的数据接口。

4. 发明申请

US20110231858A1 BURST ACCESS PROTOCOL 有权
公开(公告)号：US20110231858A1
公开(公告)日：2011-09-22
申请号：US12887206
申请日：2010-09-21
申请人： Ramkumar Sampathkumar , Phani B. Avadhanam , Siddharth Jayaraman , Michael Bailey
发明人： Ramkumar Sampathkumar , Phani B. Avadhanam , Siddharth Jayaraman , Michael Bailey
IPC分类号： G06F9/46
CPC分类号： G06F9/4403 , G06F9/4405
摘要： Methods and systems provide a burst access protocol that enables efficient transfer of data between a first and a second processor via a data interface whose access set up time could present a communication bottleneck. Data, indices, and/or instructions are transmitted in a static table from the first processor and stored in memory accessible to the second processor. Later, the first processor transmit to the second processor a dynamic table which specifies particular data, indices and/or instructions within the static table that are to be implemented by the second processor. The second processor uses the dynamic table to implement the identified particular subset of data, indices and/or instructions. By transmitting the bulk of data, indices and/or instructions to the second processor in a large static table, the burst access protocol enables efficient use of data interfaces which can transmit large amounts of information, but require relatively long access setup times.
摘要翻译：方法和系统提供突发接入协议，其能够经由其接入建立时间可能呈现通信瓶颈的数据接口在第一和第二处理器之间有效地传送数据。数据，索引和/或指令在静态表中从第一处理器发送并存储在第二处理器可访问的存储器中。之后，第一处理器向第二处理器发送动态表，该动态表指定要由第二处理器实现的静态表内的特定数据，索引和/或指令。第二处理器使用动态表来实现所识别的数据，索引和/或指令的特定子集。通过将大量数据，索引和/或指令发送到大型静态表中的第二处理器，突发存取协议能够有效利用可传输大量信息但需要相对长的访问建立时间的数据接口。

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