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1. 发明申请

US20110051519A1 Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 审中-公开
标题翻译：新型基于NAND的混合NVM设计，将NAND和NOR集成在1-die与串行接口中
公开(公告)号：US20110051519A1
公开(公告)日：2011-03-03
申请号：US12807080
申请日：2010-08-27
申请人： Peter W. Lee , Kesheng Wang , Fu-Chang Hsu
发明人： Peter W. Lee , Kesheng Wang , Fu-Chang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/32 , G11C7/1075
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. An enable signal defines a beginning and termination of a reading or writing operation. Reading one nonvolatile memory array may be interrupted for another operation and then resumed.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在串行接口上传输。串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码启用信号定义读取或写入操作的开始和结束。读取一个非易失性存储器阵列可能被中断用于另一个操作，然后恢复。

2. 发明授权

US08996785B2 NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 有权
标题翻译：基于NAND的混合NVM设计，将NAND和NOR与1串口串行接口集成
公开(公告)号：US08996785B2
公开(公告)日：2015-03-31
申请号：US12807997
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/00 , G11C16/32 , G11C16/04
CPC分类号： G11C16/32 , G11C16/0408
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在串行接口上传输。串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

3. 发明申请

US20110072201A1 Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 有权
标题翻译：新型基于NAND的混合NVM设计，将NAND和NOR集成在1-die与串行接口中
公开(公告)号：US20110072201A1
公开(公告)日：2011-03-24
申请号：US12807997
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/02 , G11C16/06
CPC分类号： G11C16/32 , G11C16/0408
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在串行接口上传输。串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

4. 发明授权

US08775719B2 NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
标题翻译：基于NAND的混合NVM设计，在单模并行接口中集成NAND和NOR
公开(公告)号：US08775719B2
公开(公告)日：2014-07-08
申请号：US12807996
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1075 , G11C2216/22
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在并行接口上传输。并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

5. 发明申请

US20110072200A1 Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
标题翻译：新型基于NAND的混合NVM设计，将NAND和NOR集成在1模并行接口中
公开(公告)号：US20110072200A1
公开(公告)日：2011-03-24
申请号：US12807996
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/02 , G11C16/06
CPC分类号： G11C16/10 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1075 , G11C2216/22
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在并行接口上传输。并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

6. 发明授权

US08149622B2 Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage 失效
标题翻译：具有基于NAND的NOR和NAND闪存的存储器系统和集成在一个芯片中的SRAM用于混合数据，代码和高速缓存存储
公开(公告)号：US08149622B2
公开(公告)日：2012-04-03
申请号：US12701509
申请日：2010-02-05
申请人： Peter Wung Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter Wung Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C7/1075 , G11C8/16
摘要： A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.
摘要翻译：存储器系统包括NAND闪存，NOR闪存和单个芯片上的SRAM存储器。 NAND和NOR存储器都由相同的NAND制造工艺和NAND单元制造。三个存储器共享相同的地址总线，数据总线和单个芯片的引脚。地址总线是双向的，用于接收代码，数据和地址以及发送输出。数据总线也是双向的，用于接收和发送数据。一个外部芯片使能引脚和一个外部输出使能引脚由三个存储器共享，以减少单个芯片所需的引脚数。 NAND和NOR存储器都具有双读取页面缓冲器和用于Read-While-Load和Write-While-Program-Write操作的双写入页面缓冲器，以分别加速读取和写入操作。存储器映射方法用于选择不同的存储器，状态寄存器和双读或写页缓冲器。

7. 发明申请

US20100329011A1 MEMORY SYSTEM HAVING NAND-BASED NOR AND NAND FLASHES AND SRAM INTEGRATED IN ONE CHIP FOR HYBRID DATA, CODE AND CACHE STORAGE 失效
标题翻译：具有基于NAND的NAND和NAND闪存的存储器系统和集成在一个芯片中的SRAM用于混合数据，代码和缓存存储
公开(公告)号：US20100329011A1
公开(公告)日：2010-12-30
申请号：US12701509
申请日：2010-02-05
申请人： Peter Wung Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter Wung Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C7/1075 , G11C8/16
摘要： A memory system includes a NAND flash memory, a NOR flash memory and a SRAM manufactured on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.
摘要翻译：存储器系统包括NAND闪存，NOR闪存和在单个芯片上制造的SRAM。 NAND和NOR存储器都由相同的NAND制造工艺和NAND单元制造。三个存储器共享相同的地址总线，数据总线和单个芯片的引脚。地址总线是双向的，用于接收代码，数据和地址以及发送输出。数据总线也是双向的，用于接收和发送数据。一个外部芯片使能引脚和一个外部输出使能引脚由三个存储器共享，以减少单个芯片所需的引脚数。 NAND和NOR存储器都具有双读取页面缓冲器和用于Read-While-Load和Write-While-Program-Write操作的双写入页面缓冲器，以分别加速读取和写入操作。存储器映射方法用于选择不同的存储器，状态寄存器和双读或写页缓冲器。

8. 外观设计

USD986275S1 Display screen or portion thereof with graphical user interface 有权
公开(公告)号：USD986275S1
公开(公告)日：2023-05-16
申请号：US29774664
申请日：2021-03-18
申请人： Jin Huang , Kesheng Wang , Gang Huang , Yin Yao , Zhengke Hou
设计人： Jin Huang , Kesheng Wang , Gang Huang , Yin Yao , Zhengke Hou
摘要： FIG. 1 is a front view of the first image in a sequence for a display screen or portion thereof with graphical user interface, showing our new design; and,
FIG. 2 is the second image thereof.
The appearance of the transitional image sequentially transitions between the images shown in FIGS. 1-2. The process or period in which one image transitions to another image forms no part of the claimed design.
The outermost broken line in the figures illustrates a portion of a display device that forms no part of the claimed design. The inner broken line next to the outermost broken line in the figures illustrates a portion of a display screen that forms no part of the claimed design. Similarly, the remaining broken lines represent features of the graphical user interface that form no part of the claimed design.

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