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1. 发明申请

US20110087932A1 Method and System for Detecting a Failure In an Error Correcting Unit 有权
标题翻译：在错误纠正单元中检测故障的方法和系统
公开(公告)号：US20110087932A1
公开(公告)日：2011-04-14
申请号：US12772423
申请日：2010-05-03
申请人： Peter Sautter , Harald Tschentscher , Carsten Gebauer , Berthold Fehrenbacher , Roy M. Haley , Alexandre Palus , Charles Ming-Fong Tsai , Venkata Kishore Gadde , Hoi-Man Low
发明人： Peter Sautter , Harald Tschentscher , Carsten Gebauer , Berthold Fehrenbacher , Roy M. Haley , Alexandre Palus , Charles Ming-Fong Tsai , Venkata Kishore Gadde , Hoi-Man Low
IPC分类号： G06F11/07
CPC分类号： G06F11/2215
摘要： In order to detect a faulty error correcting unit (2) in an embedded system, wherein the error correcting unit (2) receives output data from a data source (20) and determines, whether the received data are incorrect, and wherein if the received data are incorrect, the error correcting unit (2) is expected to correct at least one error within the received data, output the corrected data and manipulate an error vector (4), a method and a system (Ia) are suggested that enable to compare the output data of the error correcting unit (2) with at least one reference data, wherein the at least one reference data originate at least indirectly from the data source (20). Both, the error vector (4) and the result of the comparison are input to a plausibility test in order to decide, whether the error correcting unit (2) is faulty. According to the result of the plausibility test, a failure vector (7) is manipulated in order to indicate whether a failure in the error correcting unit (2) is detected.
摘要翻译：为了检测嵌入式系统中的故障纠错单元（2），其中纠错单元（2）从数据源（20）接收输出数据，并确定接收到的数据是否不正确，并且其中如果接收到数据不正确，误差校正单元（2）预期校正接收到的数据中的至少一个误差，输出校正数据并操纵误差向量（4），建议方法和系统（1a），使得能够将纠错单元（2）的输出数据与至少一个参考数据进行比较，其中至少一个参考数据至少从数据源（20）间接产生。误差矢量（4）和比较结果都输入到合理性检验中，以确定误差校正单元（2）是否有故障。根据合理性试验的结果，操作故障矢量（7），以指示是否检测到纠错单元（2）中的故障。

2. 发明授权

US08423836B2 Method and system for detecting a failure in an error correcting unit 有权
标题翻译：用于检测纠错单元中的故障的方法和系统
公开(公告)号：US08423836B2
公开(公告)日：2013-04-16
申请号：US12772423
申请日：2010-05-03
申请人： Peter Sautter , Harald Tschentscher , Carsten Gebauer , Berthold Fehrenbacher , Roy M. Haley , Alexandre Palus , Charles Ming-Fong Tsai , Venkata Kishore Gadde , Hoi-Man Low
发明人： Peter Sautter , Harald Tschentscher , Carsten Gebauer , Berthold Fehrenbacher , Roy M. Haley , Alexandre Palus , Charles Ming-Fong Tsai , Venkata Kishore Gadde , Hoi-Man Low
IPC分类号： G06F11/00
CPC分类号： G06F11/2215
摘要： In order to detect a faulty error correcting unit (2) in an embedded system, wherein the error correcting unit (2) receives output data from a data source (20) and determines, whether the received data are incorrect, and wherein if the received data are incorrect, the error correcting unit (2) is expected to correct at least one error within the received data, output the corrected data and manipulate an error vector (4), a method and a system (Ia) are suggested that enable to compare the output data of the error correcting unit (2) with at least one reference data, wherein the at least one reference data originate at least indirectly from the data source (20). Both, the error vector (4) and the result of the comparison are input to a plausibility test in order to decide, whether the error correcting unit (2) is faulty. According to the result of the plausibility test, a failure vector (7) is manipulated in order to indicate whether a failure in the error correcting unit (2) is detected.
摘要翻译：为了检测嵌入式系统中的故障纠错单元（2），其中纠错单元（2）从数据源（20）接收输出数据，并确定接收到的数据是否不正确，并且其中如果接收到数据不正确，误差校正单元（2）预期校正接收到的数据中的至少一个误差，输出校正数据并操纵误差向量（4），建议方法和系统（1a），使得能够将纠错单元（2）的输出数据与至少一个参考数据进行比较，其中至少一个参考数据至少从数据源（20）间接产生。误差矢量（4）和比较结果都输入到合理性检验中，以确定误差校正单元（2）是否有故障。根据合理性试验的结果，操作故障矢量（7），以指示是否检测到纠错单元（2）中的故障。

3. 发明申请

US20050262403A1 Apparatus and method for single operation read-modify-write in a bit-accessible memory unit memory 审中-公开
标题翻译：用于在位可访问的存储器单元存储器中的单次操作读 - 修改 - 写入的装置和方法
公开(公告)号：US20050262403A1
公开(公告)日：2005-11-24
申请号：US11133952
申请日：2005-05-20
申请人： Alexandre Palus
发明人： Alexandre Palus
IPC分类号： G01R31/28 , G11C7/10 , G11C29/00
CPC分类号： G11C7/10 , G11C7/1006
摘要： In a bit-accessible memory, a read-modify-write instruction is replaced by an operation with a single memory access. A first mirror memory is identified by a first address OFFSET of the actual memory address. A SET signal logic process is performed when the first mirror memory is addressed. A second mirror memory is identified by a second address offset. A CLEAR signal logic process is performed when the second address offset is used. Transferring the mask used for the read-modify-write operation along with the address, a single predetermined memory location is enabled. The write data bus has logic “1”s applied to all conductors for a SET operation and all logic “0”s for the Clear operation. Only the predetermined memory location is enabled. Thus the correct logic signal is stored in the only enabled location, the predetermined location identified by the mask. In the absence of the OFFSET signal, a normal write operation is performed for the memory access.
摘要翻译：在可位访问存储器中，读 - 修改 - 写指令被具有单个存储器访问的操作所取代。第一个镜像存储器由实际存储器地址的第一个地址OFFSET来标识。当第一镜像存储器被寻址时，执行SET信号逻辑处理。第二个镜像存储器由第二个地址偏移来标识。当使用第二地址偏移时，执行CLEAR信号逻辑处理。将用于读 - 修改 - 写入操作的掩码与地址一起传输，启用单个预定存储器位置。写数据总线的逻辑“1”应用于所有导体用于SET操作，所有逻辑“0”用于清除操作。只有预定的存储位置被启用。因此，正确的逻辑信号被存储在唯一启用的位置，由掩码识别的预定位置。在没有OFFSET信号的情况下，对存储器访问执行正常的写入操作。

4. 发明申请

US20050182920A1 Apparatus and method for expedited exception handling using a dedicated port 审中-公开
标题翻译：使用专用端口进行快速异常处理的装置和方法
公开(公告)号：US20050182920A1
公开(公告)日：2005-08-18
申请号：US11057301
申请日：2005-02-11
申请人： Alexandre Palus
发明人： Alexandre Palus
IPC分类号： G06F7/38 , G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/3004 , G06F9/3861
摘要： To expedite the response to an interrupt instruction, an interrupt identification component monitors the execution unit of the central processing unit. When an interrupt instruction is identified, the interrupt identification component forwards this information through a dedicated port to the exception handler, the exception handler storing the procedures that respond to the interrupt instruction. In response to the signals from the interrupt identification unit, the exception handler forwards the responsive procedure to the central processing unit. In this manner, the execution of the interrupt procedure is expedited.
摘要翻译：为了加快对中断指令的响应，中断识别组件监视中央处理单元的执行单元。当确定中断指令时，中断标识组件通过专用端口将该信息转发到异常处理程序，异常处理程序存储响应中断指令的过程。响应于来自中断识别单元的信号，异常处理程序将响应过程转发到中央处理单元。以这种方式，加速中断程序的执行。

5. 发明申请

US20120066551A1 Run-time Verification of CPU Operation 审中-公开
标题翻译： CPU运行的运行时验证
公开(公告)号：US20120066551A1
公开(公告)日：2012-03-15
申请号：US12883034
申请日：2010-09-15
申请人： Alexandre Palus , Karl Friedrich Greb , Balatripura Sodemma Chavali
发明人： Alexandre Palus , Karl Friedrich Greb , Balatripura Sodemma Chavali
IPC分类号： G06F11/07
CPC分类号： G06F11/28 , G06F11/3636
摘要： Safe operation in a processor may be verified by making use of an execution trace module that is normally only used for testing and software development. During operation of the processor in the field, a sequence of instructions may be executed the processor. A portion of the execution is traced to form a sequence of trace data. The sequence of trace data is compressed to form a checksum. The checksum is compared to a reference checksum, and an execution error is indicated when the checksum does not match the reference checksum.
摘要翻译：可以通过使用通常仅用于测试和软件开发的执行跟踪模块来验证处理器中的安全操作。在本领域中的处理器的操作期间，可以执行处理器的一系列指令。执行的一部分被跟踪以形成一系列跟踪数据。跟踪数据的序列被压缩以形成校验和。校验和与参考校验和进行比较，当校验和与参考校验和不匹配时，会显示执行错误。

6. 发明申请

US20050184752A1 Apparatus and method for automotive bus switching protection 审中-公开
标题翻译：汽车总线切换保护装置及方法
公开(公告)号：US20050184752A1
公开(公告)日：2005-08-25
申请号：US10784722
申请日：2004-02-23
申请人： Alexandre Palus
发明人： Alexandre Palus
IPC分类号： H03K19/003 , H03K19/007
CPC分类号： H04L1/24 , H03K19/0075 , H04L25/0272
摘要： In order to insure accurate transmission of logic signal, the logic signal and its complement are transmitted between a central processing unit and a peripheral unit. The logic signal and its complement are both used to reconstruct the original logic signal. When an error has occurred in either the logic signal or its complement, an EXCEPTION signal is generated.
摘要翻译：为了确保逻辑信号的精确传输，逻辑信号及其补码在中央处理单元和外围单元之间传输。逻辑信号及其补码都用于重建原始逻辑信号。当逻辑信号或其补码发生错误时，会产生异常信号。

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