专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050282503A1 Combined matching and filter circuit 有权
标题翻译：组合匹配和滤波电路
公开(公告)号：US20050282503A1
公开(公告)日：2005-12-22
申请号：US10872947
申请日：2004-06-21
申请人： Peter Onno , Rajanish , Nitin Jain , Christopher Weigand
发明人： Peter Onno , Rajanish , Nitin Jain , Christopher Weigand
IPC分类号： H03H2/00 , H03H7/01 , H03H7/09 , H03H7/38 , H04B1/00
CPC分类号： H03H7/1758 , H03H7/0115 , H03H7/0123 , H03H7/1766 , H03H7/1783 , H03H7/1791 , H03H7/38 , H03H2001/0064 , H03H2001/0078
摘要： A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.
摘要翻译：一种组合匹配和谐波抑制电路，其具有由电路的一个或多个电容或电感元件的分裂谐振提供的增加的谐波抑制电路。在基频处，电路包括具有电容分流臂的感应串联臂。分流臂的电容可以由两个或更多个并联路径提供，每个并联路径具有串联的电容器和电感器，使得除了提供在基频处的阻抗匹配所必需的有效电容之外，由并行路径的串联谐振被拒绝。以这种方式，可以使用在基频实现阻抗匹配所需的相同数量的并联元件来实现电路的阻带中的额外零点。

2. 外观设计

USD679922S1 Greeting card outpost 有权
标题翻译：贺卡前哨
公开(公告)号：USD679922S1
公开(公告)日：2013-04-16
申请号：US29427181
申请日：2012-07-16
申请人： Christopher Weigand
设计人： Christopher Weigand

3. 外观设计

USD627580S1 Flexible fixture for greeting card and non-greeting card merchandise 有权
标题翻译：弹性夹具用于贺卡和非贺卡商品
公开(公告)号：USD627580S1
公开(公告)日：2010-11-23
申请号：US29339337
申请日：2009-06-29
申请人： Christopher Weigand , Gary Hodge , Emory Brozak, Jr.
设计人： Christopher Weigand , Gary Hodge , Emory Brozak, Jr.

4. 发明申请

US20050227643A1 Apparatus and method for detecting radio frequency transmission power levels 失效
公开(公告)号：US20050227643A1
公开(公告)日：2005-10-13
申请号：US10868123
申请日：2004-06-15
申请人： Christopher Brindle , Norbert Schmitz , Christopher Weigand
发明人： Christopher Brindle , Norbert Schmitz , Christopher Weigand
IPC分类号： H03G3/20 , H04B1/04 , H01Q11/12 , H04B1/00
CPC分类号： H04B1/04 , H03G3/3042
摘要： An apparatus and method for detecting radio frequency transmit power levels produced by a power amplifier of a wireless device is described. In one exemplary apparatus implementation, the apparatus includes a power amplifier, an antenna switch and a power amplifier detector. The power amplifier is configured to amplify a transmit signal at a desired power level. An antenna switch, is located between the power amplifier and an antenna, and is configured to switch the antenna from a receive mode to a transmit mode and vice versa. A power amplifier detector is connected to the antenna switch. The power amplifier detector is configured to receive a leakage signal from the antenna switch as a basis to detect the power level of the transmit signal.

5. 发明申请

US20100171541A1 CONSTANT PHASE DIGITAL ATTENUATOR WITH ON-CHIP MATCHING CIRCUITRY 有权
标题翻译：具有片上匹配电路的恒定相数字衰减器
公开(公告)号：US20100171541A1
公开(公告)日：2010-07-08
申请号：US12725533
申请日：2010-03-17
申请人： Wen Hui Zhang , Christopher Weigand
发明人： Wen Hui Zhang , Christopher Weigand
IPC分类号： H03H11/24
CPC分类号： H03H11/245 , H01P1/22
摘要： Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit (100) comprises an input node (102) to receive an input signal to be attenuated, an output node (104) to output an attenuated signal, a reference loss path (106) between the input node (102) and the output node (104), and an attenuation path (108) between the input node (102) and the output node (104). The reference loss path (106) comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path (108) comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit (100) is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path (106) and an effective phase length of the attenuation path (108) may be equalized to provide a constant phase when the digital attenuator circuit (100) is switched between states.
摘要翻译：各种实施例旨在提供恒定相数字衰减。在一个实施例中，数字衰减器电路（100）包括用于接收待衰减的输入信号的输入节点（102），输出衰减信号的输出节点（104），输入节点（102）和输出节点（104），以及在输入节点（102）和输出节点（104）之间的衰减路径（108）。参考损耗路径（106）包括开关元件和匹配电路以改善电压驻波比（VSWR），并且衰减路径（108）包括开关元件和衰减电路，以在数字衰减器电路（100）为从参考丢失状态切换到衰减状态。当数字衰减器电路（100）在状态之间切换时，参考损耗路径（106）的有效相位长度和衰减路径（108）的有效相位长度可以相等以提供恒定相位。

6. 发明授权

US07990201B2 Constant phase digital attenuator with on-chip matching circuitry 有权
标题翻译：具有片上匹配电路的恒相数字衰减器
公开(公告)号：US07990201B2
公开(公告)日：2011-08-02
申请号：US12725533
申请日：2010-03-17
申请人： Wen Hui Zhang , Christopher Weigand
发明人： Wen Hui Zhang , Christopher Weigand
IPC分类号： H03L5/00
CPC分类号： H03H11/245 , H01P1/22
摘要： Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit (100) comprises an input node (102) to receive an input signal to be attenuated, an output node (104) to output an attenuated signal, a reference loss path (106) between the input node (102) and the output node (104), and an attenuation path (108) between the input node (102) and the output node (104). The reference loss path (106) comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path (108) comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit (100) is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path (106) and an effective phase length of the attenuation path (108) may be equalized to provide a constant phase when the digital attenuator circuit (100) is switched between states.
摘要翻译：各种实施例旨在提供恒定相数字衰减。在一个实施例中，数字衰减器电路（100）包括用于接收待衰减的输入信号的输入节点（102），输出衰减信号的输出节点（104），输入节点（102）和输出节点（104），以及在输入节点（102）和输出节点（104）之间的衰减路径（108）。参考损耗路径（106）包括开关元件和匹配电路以改善电压驻波比（VSWR），并且衰减路径（108）包括开关元件和衰减电路，以在数字衰减器电路（100）为从参考丢失状态切换到衰减状态。当数字衰减器电路（100）在状态之间切换时，参考损耗路径（106）的有效相位长度和衰减路径（108）的有效相位长度可以相等以提供恒定相位。

7. 外观设计

USD626765S1 Flexible fixture for greeting cards and non-greeting card merchandise 有权
标题翻译：弹性夹具用于贺卡和非贺卡商品
公开(公告)号：USD626765S1
公开(公告)日：2010-11-09
申请号：US29346585
申请日：2009-11-03
申请人： Christopher Weigand , Gary Hodge , Emory Brozak, Jr.
设计人： Christopher Weigand , Gary Hodge , Emory Brozak, Jr.

8. 发明申请

US20090079489A1 CONSTANT PHASE DIGITAL ATTENUATOR WITH ON-CHIP MATCHING CIRCUITRY 审中-公开
标题翻译：具有片上匹配电路的恒定相数字衰减器
公开(公告)号：US20090079489A1
公开(公告)日：2009-03-26
申请号：US11859130
申请日：2007-09-21
申请人： Wen Hui Zhang , Christopher Weigand
发明人： Wen Hui Zhang , Christopher Weigand
IPC分类号： H03H11/24
CPC分类号： H03H11/245 , H01P1/22
摘要： Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit comprises an input node to receive an input signal to be attenuated, an output node to output an attenuated signal, a reference loss path between the input node and the output node, and an attenuation path between the input node and the output node. The reference loss path comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path and an effective phase length of the attenuation path may be equalized to provide a constant phase when the digital attenuator circuit is switched between states. Other embodiments are described and claimed.
摘要翻译：各种实施例旨在提供恒定相数字衰减。在一个实施例中，数字衰减器电路包括用于接收要衰减的输入信号的输入节点，输出衰减信号的输出节点，输入节点和输出节点之间的参考损耗路径以及输入端之间的衰减路径节点和输出节点。参考损耗路径包括开关元件和匹配电路以改善电压驻波比（VSWR），并且当数字衰减器电路从参考损耗状态切换到衰减时，衰减路径包括开关元件和衰减电路以衰减输入信号州。可以将参考损耗路径的有效相位长度和衰减路径的有效相位长度相等，以在数字衰减器电路在状态之间切换时提供恒定相位。描述和要求保护其他实施例。

9. 发明授权

US08636152B1 Greeting card outpost 有权
标题翻译：贺卡前哨
公开(公告)号：US08636152B1
公开(公告)日：2014-01-28
申请号：US13549621
申请日：2012-07-16
申请人： Christopher Weigand
发明人： Christopher Weigand
IPC分类号： A47F7/14 , A47F5/08 , A47F5/14 , A47G29/00 , A47F5/13 , A47B63/00 , A47B55/02 , A47B57/00
CPC分类号： A47F7/148 , A47B55/02 , A47B57/00 , A47B63/00 , A47F5/132 , A47F7/146 , A47F7/147
摘要： The greeting card outpost of the present disclosure and related inventions is a unique and versatile structure which maximizes the number of greeting cards which can be displayed for sale in retail areas which are limited in space. The fixture includes a plurality of adjacent vertically arranged card pockets attached to an angled support structure and standard tube frame which creates angled array of greeting cards extending outward from a front of the display and ending in a fin-like fashion at the back of the display. The novel arrangement decreases the size of space required to display the variety of greeting cards which can be accommodated upon the outpost fixture.
摘要翻译：本公开的贺卡前哨和相关发明是一种独特且多功能的结构，其使在空间有限的零售区域中可显示出售的贺卡数量最大化。固定装置包括多个相邻的垂直布置的卡槽，其附接到成角度的支撑结构和标准管框架，其形成从显示器的前部向外延伸并以显示器背面的鳍状方式延伸的倾斜阵列的贺卡。新颖的布置减少了显示可以容纳在前哨灯具上的各种贺卡所需的空间的大小。

10. 发明申请

US20070075783A1 Handset Radiofrequency Front End Module In Fine Pitch Quad Flat No Lead (FQFP-N) Package 有权
标题翻译：手机射频前端模块采用精细间距四边形无铅（FQFP-N）封装
公开(公告)号：US20070075783A1
公开(公告)日：2007-04-05
申请号：US11608559
申请日：2006-12-08
申请人： Christopher Weigand , Thomas Winslow , Richard Giacchino
发明人： Christopher Weigand , Thomas Winslow , Richard Giacchino
IPC分类号： H03F3/191
CPC分类号： H03F3/3432 , H03F1/30 , H03F1/34 , H03F3/195 , H03F3/211 , H03F3/3435 , H03F3/50 , H03F3/72 , H03F2200/111 , H03F2200/153 , H03F2200/18 , H03F2200/451 , H04B1/006 , H04B1/0458 , H04B1/12 , H04B1/48
摘要： An apparatus and method for transmitting signal, the apparatus comprising a front end telecommunications module including a power amplifier, a matching circuit coupled to the power amplifier, and a filter coupled to the matching circuit, such that a signal received by the power amplifier is transmitted to the filter through the matching circuit. The telecommunications module provides quad-band capability in a compact design.
摘要翻译：一种用于发送信号的装置和方法，该装置包括前端电信模块，其包括功率放大器，耦合到功率放大器的匹配电路和耦合到匹配电路的滤波器，使得由功率放大器接收的信号被传输通过匹配电路到滤波器。电信模块在紧凑的设计中提供四频带功能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式