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1. 发明授权

US6032233A Storage array allowing for multiple, simultaneous write accesses 失效
标题翻译：存储阵列允许多个并发写入访问
公开(公告)号：US6032233A
公开(公告)日：2000-02-29
申请号：US886304
申请日：1997-07-01
申请人： Peter Loffler , Erwin Pfeffer , Thomas Pfluger , Hans-Werner Tast
发明人： Peter Loffler , Erwin Pfeffer , Thomas Pfluger , Hans-Werner Tast
IPC分类号： G11C8/16 , G06F12/02
CPC分类号： G11C8/16
摘要： A set of storage devices together with a method for storing data to the storage devices and retrieving data from the storage devices is presented. The set of storage devices provide the function of a multi-writeport cell through the use of a set of single-writeport cells. The storage devices allow for multiple write accesses. Information contained in the set of storage device is represented by all of the devices together. The stored information may be retrieved via a read operation which accesses a subset of the set of storage devices. A write operation is a staged operation: First, the contents of all of the storage devices which are not to be modified are read. Next, the values that are to be written to a subset B of the set of storage devices are calculated in a way that the contents and the values of subset B together represent the desired result.
摘要翻译：提供一组存储设备以及用于将数据存储到存储设备并从存储设备检索数据的方法。该组存储设备通过使用一组单写入单元提供多写入单元的功能。存储设备允许多次写访问。包含在该组存储设备中的信息由所有设备一起表示。存储的信息可以通过访问该组存储设备的子集的读取操作来检索。写入操作是分阶段操作：首先，读取所有不被修改的存储设备的内容。接下来，以将子集B的内容和值一起表示期望结果的方式计算要写入该组存储装置的子集B的值。

2. 发明授权

US5761734A Token-based serialisation of instructions in a multiprocessor system 失效
标题翻译：多处理器系统中基于令牌的指令序列化
公开(公告)号：US5761734A
公开(公告)日：1998-06-02
申请号：US689762
申请日：1996-08-13
申请人： Erwin Pfeffer , Klaus-Joerg Getzlaff , Ute Gaertner , Hans-Werner Tast
发明人： Erwin Pfeffer , Klaus-Joerg Getzlaff , Ute Gaertner , Hans-Werner Tast
IPC分类号： G06F9/46 , G06F12/10 , G06F12/16
CPC分类号： G06F9/52 , G06F12/1072
摘要： A process is disclosed to serialize instructions that are to be processed serially in a multiprocessor system, with the use of a token, where the token can be assigned on request to one of the processors, which thereupon has the right to execute the command. If the command consists of dristibuted tasks, the token remains blocked until the last dependent task belonging to the command has also been executed. It is only then that the token can be assigned to another instruction. Moreover, a device is described to manage this token, which features three states: a first state, in which the token is available, a second state, in which the token is assigned to one of the processors, and a third state, in which the token is blocked, because dependent tasks still have to be carried out. Moreover, a circuit is disclosed with which the token principle that is introduced can be implemented in a simple manner. The token is only available if none of the processors i is in possession of the token and if no dependent task is pending at any of the processors. The OR chaining of signals to form a signal C which is set if the token is not available represents the basic circuitry with which the serialisation of commands consisting of distributed tasks is carried out. The invention is applied particularly in the case of commands such as IPTE (invalidate page-table entry) and SSKE (set storage key extended), which modify the address translation tables in the memory that are used in common by all processors.
摘要翻译：公开了一种过程，其使用令牌来序列化要在多处理器系统中串行处理的指令，其中令牌可以根据请求分配给一个处理器，其中有一个执行命令。如果命令由dristibuted任务组成，令牌将保持阻塞，直到属于命令的最后一个任务也已被执行。只有令牌可以分配给另一个指令。此外，描述了一种用于管理该令牌的设备，其特征在于三个状态：其中令牌可用的第一状态，其中将令牌分配给处理器之一的第二状态和第三状态，其中令牌被阻止，因为依赖的任务仍然需要执行。此外，公开了可以以简单的方式实现引入的令牌原理的电路。该令牌仅在没有任何一个处理器拥有该令牌并且任何一个处理器中未依赖任务的情况下可用。如果令牌不可用，则形成信号C的OR链接形成表示执行由分散任务组成的命令的串行化的基本电路。本发明特别适用于诸如IPTE（无效页表条目）和SSKE（设置存储密钥扩展）的命令的情况，其修改由所有处理器共同使用的存储器中的地址转换表。

3. 发明授权

US6108771A Register renaming with a pool of physical registers 失效
标题翻译：使用一个物理寄存器池重命名
公开(公告)号：US6108771A
公开(公告)日：2000-08-22
申请号：US15870
申请日：1998-01-29
申请人： Ute Gaertner , Klaus Jorg Getzlaff , Erwin Pfeffer , Hans-Werner Tast
发明人： Ute Gaertner , Klaus Jorg Getzlaff , Erwin Pfeffer , Hans-Werner Tast
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.
摘要翻译：描述了允许使用最少数量的物理寄存器的无序处理系统中的寄存器重命名和分配的系统和方法。链接列表允许将表示相应逻辑寄存器的某个实例的物理寄存器连接到表示相同逻辑寄存器的下一个实例的物理寄存器。通过添加和删除此链接列表中的链接，可以动态地管理物理寄存器到逻辑寄存器的分配。表示推测实例的物理寄存器和表示顺序实例的物理寄存器都被一起管理。这是通过一个顺序列表来完成的，它列出了实际表示机器的架构状态的物理寄存器。

4. 发明申请

US20120011341A1 Load Page Table Entry Address Instruction Execution Based on an Address Translation Format Control Field 有权
标题翻译：基于地址转换格式控制字段加载页表输入地址指令执行
公开(公告)号：US20120011341A1
公开(公告)日：2012-01-12
申请号：US13234374
申请日：2011-09-16
申请人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Gustav E. Sittmann
发明人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Gustav E. Sittmann
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/651 , G06F2212/652
摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.
摘要翻译：提供了为计算机系统的机器结构定义的加载页表项地址函数。在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。基于M场的内容，获得具有至少一个分段表的地址转换表的层次结构的初始起始地址。基于获得的初始起始地址，执行动态地址转换，直到获得页表项。页表入口地址保存在识别的第一个通用寄存器中。

5. 发明授权

US08082405B2 Dynamic address translation with fetch protection 有权
标题翻译：动态地址转换带保护
公开(公告)号：US08082405B2
公开(公告)日：2011-12-20
申请号：US11972682
申请日：2008-01-11
申请人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles E. Webb
发明人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles E. Webb
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1475 , G06F12/1036 , G06F12/109
摘要： In an enhanced dynamic address translation facility a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are used to access a segment table entry containing a format control field and an access validity field. If the format control field is enabled, the segment table entry further contains an access control field and a fetch protection field and a segment-frame absolute address. Fetch operations from the desired block of data are permitted if the program access key associated with the virtual address is equal to the segment access control field.
摘要翻译：在增强型动态地址转换装置中，使用要转换的虚拟地址和转换表层级的转换表的初始起始地址来访问包含格式控制字段和访问有效性字段的段表条目。如果格式控制字段被使能，则段表条目还包含访问控制字段和取指保护字段和段帧绝对地址。如果与虚拟地址相关联的程序访问密钥等于段访问控制字段，则允许从所需数据块获取操作。

6. 发明授权

US07975182B2 Method, system and computer program product for generating trace data 失效
标题翻译：用于生成跟踪数据的方法，系统和计算机程序产品
公开(公告)号：US07975182B2
公开(公告)日：2011-07-05
申请号：US12036430
申请日：2008-02-25
申请人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
发明人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F11/3461 , G06F2201/885
摘要： There is provided a method, system and computer program product for generating trace data related to a data processing system event. The method includes: receiving an instruction relating to the system event from a location in the system; determining a minimum number of trace segment records required to record instruction information; and creating a trace segment table including the number of trace segment records, the number of trace segment records including at least one instruction record.
摘要翻译：提供了一种用于生成与数据处理系统事件相关的跟踪数据的方法，系统和计算机程序产品。该方法包括：从系统中的位置接收与系统事件有关的指令; 确定记录指令信息所需的跟踪段记录的最小数量; 并创建包括跟踪段记录的数量的跟踪段表，包括至少一个指令记录的跟踪段记录的数目。

7. 发明申请

US20090216992A1 DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER 有权
标题翻译：动态地址翻译与翻译例外的合格者
公开(公告)号：US20090216992A1
公开(公告)日：2009-08-27
申请号：US12037268
申请日：2008-02-26
申请人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer
发明人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer
IPC分类号： G06F12/10
CPC分类号： G06F12/0284 , G06F3/0604 , G06F3/0667 , G06F3/067 , G06F9/455 , G06F12/10 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/1032 , G06F2212/152 , G06F2212/50 , G06F2212/652 , G06F2212/657
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。虚拟地址的动态地址转换进行。响应于在动态地址转换期间发生的翻译中断，比特被存储在转换异常限定符（TXQ）字段中，以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。

8. 发明申请

US20090182974A1 DYNAMIC ADDRESS TRANSLATION WITH ACCESS CONTROL 有权
标题翻译：动态地址翻译与访问控制
公开(公告)号：US20090182974A1
公开(公告)日：2009-07-16
申请号：US11972682
申请日：2008-01-11
申请人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles E. Webb
发明人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles E. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1475 , G06F12/1036 , G06F12/109
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。基于原始地址，获得包含格式控制字段和访问有效性字段的段表条目。如果启用格式控制和访问有效性，则段表条目还包含访问控制和提取保护字段以及段帧绝对地址。仅当访问控制字段与由程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许对数据块进行存储操作。只有当与虚拟地址相关联的程序访问密钥等于段访问控制字段时，才允许从所需数据块获取操作。

9. 发明申请

US20090182964A1 DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL 有权
标题翻译：动态地址翻译与格式控制
公开(公告)号：US20090182964A1
公开(公告)日：2009-07-16
申请号：US11972706
申请日：2008-01-11
申请人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
发明人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1009 , G06F2212/1044 , G06F2212/652
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。虚拟地址的索引部分用于引用转换表中的条目。如果启用格式控制字段，则从转换表条目获得主存储器中的大数据块的帧地址。大块数据是至少1M字节的块。然后将帧地址与虚拟地址的偏移部分组合，以在主存储器中的大量数据块内形成期望的数据块的转换地址。然后访问由翻译的地址寻址的期望的大量数据。

10. 发明授权

US06418522B1 Translation lookaside buffer for virtual memory systems 有权
标题翻译：用于虚拟内存系统的翻译后备缓冲区
公开(公告)号：US06418522B1
公开(公告)日：2002-07-09
申请号：US09501741
申请日：2000-02-11
申请人： Ute Gaertner , John MacDougall , Erwin Pfeffer , Kerstin Schelm
发明人： Ute Gaertner , John MacDougall , Erwin Pfeffer , Kerstin Schelm
IPC分类号： G06F1210
CPC分类号： G06F12/1027 , G06F2212/681
摘要： The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit. Thus, the same information is used as a tag information in the lower-level sub-unit and is used herein as a quick reference in any look-up operation in order to find the absolute address of the concerned virtual address. Further, the commonly used status bits, like; e.g., valid bits, are used in both TLB structures, too.
摘要翻译：由本发明构成的基本思想是提供一种有利地使用两个缓冲器，小的第一级TLB1和较大的第二级TLB2的翻译后备缓冲器（TLB）装置。当所需的虚拟地址不包含在第一级TLB中时，第二级TLB将地址信息馈送到第一级TLB。根据本发明，第二级TLB有利地包括两个n路组合关联子单元，其中一个较高级别单元覆盖一些较高级地址转换级别，而另一级单元覆盖一些较低级别的地址转换级别级别翻译水平。根据本发明，一些地址信息例如保持一些中间虚拟地址（MLVA）位，即8位，能够用作覆盖上位子单元的地址范围的索引地址。因此，相同的信息用作下级子单元中的标签信息，并且在本文中用作任何查找操作中的快速参考，以便找到相关虚拟地址的绝对地址。此外，常用的状态位，如; 例如有效位也用在两个TLB结构中。

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