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1. 发明授权

US07126424B2 Interface circuit for connecting to an output of a frequency converter 失效
标题翻译：用于连接变频器输出的接口电路
公开(公告)号：US07126424B2
公开(公告)日：2006-10-24
申请号：US10482720
申请日：2002-07-02
申请人： Peter Klein , Bernhard Lustig , Dieter Sewald
发明人： Peter Klein , Bernhard Lustig , Dieter Sewald
IPC分类号： H03F3/45
CPC分类号： H03F3/45677 , H03F2200/372 , H03F2203/45028 , H03F2203/45298 , H03F2203/45418 , H03F2203/45424
摘要： In an interface circuit for connection to an output of a frequency converter, at least two current paths are coupled to one another in parallel. Each current path includes at least one cascode stage for signal processing. The circuit compensates for DC voltage offsets of the frequency converter, and has a gain ratio that can be changed over for signals with a large dynamic range.
摘要翻译：在用于连接到变频器的输出的接口电路中，至少两个电流路径彼此并联耦合。每个电流路径包括用于信号处理的至少一个共源共栅级。该电路补偿变频器的直流电压偏移，并且具有可以对具有大动态范围的信号进行改变的增益比。

2. 发明申请

US20050077962A1 Interface circuit for connecting to an output of a frequency converter 失效
标题翻译：用于连接变频器输出的接口电路
公开(公告)号：US20050077962A1
公开(公告)日：2005-04-14
申请号：US10482720
申请日：2002-07-02
申请人： Peter Klein , Bernhard Lustig , Dieter Sewald
发明人： Peter Klein , Bernhard Lustig , Dieter Sewald
IPC分类号： H03F3/45
CPC分类号： H03F3/45677 , H03F2200/372 , H03F2203/45028 , H03F2203/45298 , H03F2203/45418 , H03F2203/45424
摘要： In an interface circuit for connection to an output of a frequency converter, at least two current paths are coupled to one another in parallel. Each current path includes at least one cascode stage for signal processing. The circuit compensates for DC voltage offsets of the frequency converter, and has a gain ratio that can be changed over for signals with a large dynamic range.
摘要翻译：在用于连接到变频器的输出的接口电路中，至少两个电流路径彼此并联耦合。每个电流路径包括用于信号处理的至少一个共源共栅级。该电路补偿变频器的直流电压偏移，并且具有可以对具有大动态范围的信号进行改变的增益比。

3. 发明授权

US06171937B2 Process for producing an MOS transistor 失效
标题翻译：用于制造MOS晶体管的工艺
公开(公告)号：US06171937B2
公开(公告)日：2001-01-09
申请号：US09091150
申请日：1998-06-09
申请人： Bernhard Lustig
发明人： Bernhard Lustig
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/28132 , H01L29/41783 , H01L29/42376 , H01L29/42384
摘要： A MOS transistor has a gate electrode (33) having a T-shaped cross-section. The gate length is defined in a first structuring step by a spacer technique. The area of the gate electrode in the upper region is defined in a second structuring step. The MOS transistor can be produced with a channel length of less than 100 nm.
摘要翻译： MOS晶体管具有具有T形横截面的栅电极（33）。栅极长度通过间隔物技术在第一结构化步骤中定义。在第二结构化步骤中限定上部区域中的栅极电极的面积。可以制造具有小于100nm的沟道长度的MOS晶体管。

4. 发明授权

US5705414A Method for producing a gate electrode for an MOS structure 失效
标题翻译：用于制造用于MOS结构的栅电极的方法
公开(公告)号：US5705414A
公开(公告)日：1998-01-06
申请号：US779944
申请日：1996-12-23
申请人： Bernhard Lustig
发明人： Bernhard Lustig
IPC分类号： H01L29/78 , H01L21/28 , H01L21/265
CPC分类号： H01L21/28132 , Y10S438/947
摘要： A gate electrode for an MOS structure, such as a short-channel MOS transistor, is produced. First, a hard mask is created, using a spacer of the material of the gate electrode as the etching mask, and the hard mask is used to structure the gate electrode. The method is suitable particularly for the production of gate electrodes with very thin gate dielectrics with channel lengths below 100 nm.
摘要翻译：制造用于MOS结构的栅电极，例如短沟道MOS晶体管。首先，使用栅电极的材料的间隔物作为蚀刻掩模来形成硬掩模，并且使用硬掩模来构造栅电极。该方法特别适用于生产具有非常薄的栅极电介质的栅电极，其沟道长度低于100nm。

5. 发明授权

US5253209A Integrated semiconductor memory 失效
标题翻译：集成半导体存储器
公开(公告)号：US5253209A
公开(公告)日：1993-10-12
申请号：US736468
申请日：1991-07-26
申请人： Kurt Hoffmann , Oskar Kowarik , Rainer Kraus , Bernhard Lustig , Hans D. Oberle
发明人： Kurt Hoffmann , Oskar Kowarik , Rainer Kraus , Bernhard Lustig , Hans D. Oberle
IPC分类号： G11C11/401 , G01R31/28 , G11C11/4094 , G11C11/4096 , G11C29/00 , G11C29/18 , G11C29/34
CPC分类号： G11C29/18 , G11C11/4094 , G11C11/4096
摘要： An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.
摘要翻译：集成半导体存储器包括具有以矩阵形式设置的存储单元的存储单元区，字线和内部位线，形成用于触发存储单元的内部位线对。内部加权电路各自分配给内部位线对中的相应一个。外部一对位线通常被分配给内部位线。分离晶体管对分别被分配给内部位线对中的相应一个，用于将各个内部位线对与外部位线对电气分离。位线解码器触发分离晶体管对。提供外部加权电路。鉴别器装置和预充电装置连接到外部位线对。每对内部位线的内部位线彼此分开触发。每对内部位线的内部位线彼此分开连接到外部位线对。

6. 发明授权

US4922134A Testable redundancy decoder of an integrated semiconductor memory 失效
标题翻译：集成半导体存储器的可测试冗余解码器
公开(公告)号：US4922134A
公开(公告)日：1990-05-01
申请号：US309386
申请日：1989-02-10
申请人： Kurt Hoffmann , Oskar Kowarik , Rainer Kraus , Bernhard Lustig , Hans-Dieter Oberle
发明人： Kurt Hoffmann , Oskar Kowarik , Rainer Kraus , Bernhard Lustig , Hans-Dieter Oberle
IPC分类号： G11C29/00 , G11C29/04
CPC分类号： G11C29/785
摘要： A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as at least one charging transistor, comprising, in each of the decoder stages, an addressing circuit connected to and between the switching transistor and the separable connection of the respective decoder stages, the addressing circuit being electrically simulatable when the respective separable connection is in the intact condition thereof.
摘要翻译：一种集成半导体存储器的冗余解码器，其具有包含开关晶体管的多个解码器级和具有可分离连接断开和完整的各自条件的可分离连接，以及至少一个充电晶体管，包括：解码器级，连接到开关晶体管和各个解码器级的可分离连接之间的寻址电路，当相应的可分离连接处于其完整状态时，寻址电路可电可模拟。

7. 发明授权

US06600200B1 MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors 有权
标题翻译： MOS晶体管，制造MOS晶体管的方法和制造两个互补MOS晶体管的方法
公开(公告)号：US06600200B1
公开(公告)日：2003-07-29
申请号：US09645762
申请日：2000-08-25
申请人： Bernhard Lustig , Herbert Schäfer , Lothar Risch
发明人： Bernhard Lustig , Herbert Schäfer , Lothar Risch
IPC分类号： H01L2906
CPC分类号： H01L21/823807 , H01L21/74 , H01L29/1083
摘要： A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.
摘要翻译： MOS晶体管及其制造方法包括在半导体衬底中制造由第一导电类型掺杂的阱。掺杂浓度小于1017cm-3的外延层设置在掺杂阱的表面上。由第二导电类型掺杂的与第一导电类型相反的源极/漏极区和沟道区设置在外延层中，并且它们的深度小于或等于外延层的厚度。还提供了制造两个互补MOS晶体管的方法。

8. 发明授权

US05998807A Integrated CMOS circuit arrangement and method for the manufacture thereof 失效
标题翻译：集成CMOS电路布置及其制造方法
公开(公告)号：US05998807A
公开(公告)日：1999-12-07
申请号：US925672
申请日：1997-09-09
申请人： Bernhard Lustig , Herbert Schaefer , Martin Franosch
发明人： Bernhard Lustig , Herbert Schaefer , Martin Franosch
IPC分类号： H01L21/8238 , H01L21/8256 , H01L27/092 , H01L27/12 , H01L29/786 , H01L29/76
CPC分类号： H01L27/092 , H01L21/8256 , H01L27/1203
摘要： Semiconductor islands respectively comprise at least a Si.sub.1-x Ge.sub.x layer and a distorted silicon layer that exhibits essentially the same lattice constant as the Si.sub.1-x Ge.sub.x layer are formed on an insulating layer that is located on a carrier plate. The semiconductor islands are preferably formed by selective epitaxy and comprise p-channel MOS transistors and/or n-channel MOS transistors.
摘要翻译：半导体岛分别至少包含Si1-xGex层和在位于载体板上的绝缘层上形成与Si1-xGex层基本相同的晶格常数的失真硅层。半导体岛优选通过选择性外延形成并且包括p沟道MOS晶体管和/或n沟道MOS晶体管。

9. 发明授权

US6159815A Method of producing a MOS transistor 有权
标题翻译：制造MOS晶体管的方法
公开(公告)号：US6159815A
公开(公告)日：2000-12-12
申请号：US269311
申请日：1999-06-04
申请人： Bernhard Lustig , Herbert Schafer , Martin Franosch
发明人： Bernhard Lustig , Herbert Schafer , Martin Franosch
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66636 , H01L21/823864
摘要： In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.
摘要翻译： PCT No.PCT / DE97 / 01933 Sec。 371日期1999年6月4日第 102（e）1999年6月4日PCT PCT 1996年9月3日PCT公布。公开号WO98 / 13865 日期1998年4月2日为了生产具有HDD配置文件和LDD配置文件的MOS晶体管，首先在LDD配置文件的区域中形成HDD配置文件，然后是LDD配置文件，以生成陡峭的掺杂剂配置文件。 LDD分布优选通过蚀刻和原位掺杂的选择性外延生长。

10. 再颁专利

USRE36061E Integrated semiconductor memory 失效
标题翻译：集成半导体存储器
公开(公告)号：USRE36061E
公开(公告)日：1999-01-26
申请号：US542360
申请日：1995-10-12
申请人： Kurt Hoffmann , Oskar Kowarik , Rainer Kraus , Bernhard Lustig , Hans Dieter Oberle
发明人： Kurt Hoffmann , Oskar Kowarik , Rainer Kraus , Bernhard Lustig , Hans Dieter Oberle
IPC分类号： G11C11/4094 , G11C11/4096 , G11C29/18 , G11C29/30 , G11C29/00
CPC分类号： G11C29/30 , G11C11/4094 , G11C11/4096 , G11C29/18
摘要： An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.
摘要翻译：集成半导体存储器包括具有以矩阵形式设置的存储单元的存储单元区，字线和内部位线，形成用于触发存储单元的内部位线对。内部加权电路各自分配给内部位线对中的相应一个。外部一对位线通常被分配给内部位线。分离晶体管对分别被分配给内部位线对中的相应一个，用于将各个内部位线对与外部位线对电气分离。位线解码器触发分离晶体管对。提供外部加权电路。鉴别器装置和预充电装置连接到外部位线对。每对内部位线的内部位线彼此分开触发。每对内部位线的内部位线彼此分开连接到外部位线对。

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