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1. 发明授权

US06911380B2 Method of forming silicon on insulator wafers 失效
标题翻译：在绝缘体晶圆上形成硅的方法
公开(公告)号：US06911380B2
公开(公告)日：2005-06-28
申请号：US10199123
申请日：2002-07-22
申请人： Peter G. Tolchinsky , Irwin Yablok , Mohamad A. Shaheen
发明人： Peter G. Tolchinsky , Irwin Yablok , Mohamad A. Shaheen
IPC分类号： H01L21/762 , H01L21/44
CPC分类号： H01L21/76254 , H01L21/76243 , H01L21/76256 , H01L21/76262
摘要： A method is provided for fabricating an SOI water. This may involve forming a silicon substrate and implanting oxygen into the substrate. Damaged portions of the implanted silicon may be healed/cured by CMP or anneal, for example. An epi layer may then be deposited over the healed/cured regions of the substrate. The substrate may then be annealed to form an insulative layer. The wafer may be thinned to provide the proper thickness of the epi layer.
摘要翻译：提供了制造SOI水的方法。这可能涉及形成硅衬底并将氧注入到衬底中。植入的硅的损伤部分可以例如通过CMP来愈合/固化或退火。然后可以将epi层沉积在衬底的愈合/固化区域上。然后可以将衬底退火以形成绝缘层。可以使晶片变薄以提供外延层的适当厚度。

2. 发明申请

US20090096025A1 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer 审中-公开
标题翻译：用于制造具有蚀刻停止层的绝缘体上硅（SOI）晶片的方法
公开(公告)号：US20090096025A1
公开(公告)日：2009-04-16
申请号：US12316737
申请日：2008-12-15
申请人： Peter G. Tolchinsky , Martin D. Giles , Michael L. McSwiney , Mohamad Shaheen , Irwin Yablok
发明人： Peter G. Tolchinsky , Martin D. Giles , Michael L. McSwiney , Mohamad Shaheen , Irwin Yablok
IPC分类号： H01L27/00
CPC分类号： H01L21/26533 , H01L21/76243
摘要： Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
摘要翻译：公开了具有覆盖掩埋氧化物层的蚀刻停止层的绝缘体上硅（SOI）晶片的实施例以及其制造方法的实施例。蚀刻停止层可以包括氮化硅，氮掺杂二氧化硅或氮氧化硅，以及这些材料的某些组合。描述和要求保护其他实施例。

3. 发明授权

US07378331B2 Methods of vertically stacking wafers using porous silicon 有权
标题翻译：使用多孔硅垂直堆叠晶圆的方法
公开(公告)号：US07378331B2
公开(公告)日：2008-05-27
申请号：US11025131
申请日：2004-12-29
申请人： Mohamad Shaheen , Peter G. Tolchinsky , Irwin Yablok , Scott R. List
发明人： Mohamad Shaheen , Peter G. Tolchinsky , Irwin Yablok , Scott R. List
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L24/81 , H01L21/6835 , H01L21/76259 , H01L25/0657 , H01L25/50 , H01L2224/81001 , H01L2224/81801 , H01L2924/01033 , H01L2924/14
摘要： A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.
摘要翻译：一种提供三维（3-D）IC晶片工艺流程的方法和制品。在一些实施例中，所述方法和制品包括将多层晶片的器件层接合到另一多层晶片的器件层以形成键合的器件层对，所述多层晶片中的每一个在多孔硅层上包括硅层（SiOPSi），其中所述器件层形成在所述硅层中，通过分离所述多孔硅层之一将所述一对器件层与所述硅衬底中的一个分离，并且将所述一对器件层与所述多个硅层分离通过分离另一个多孔硅层来提供剩余的硅衬底以提供垂直堆叠的晶片。

4. 发明授权

US07491988B2 Transistors with increased mobility in the channel zone and method of fabrication 有权
标题翻译：晶体管在沟道区域的迁移率增加和制造方法
公开(公告)号：US07491988B2
公开(公告)日：2009-02-17
申请号：US10880311
申请日：2004-06-28
申请人： Peter G. Tolchinsky , Mark Bohr , Irwin Yablok
发明人： Peter G. Tolchinsky , Mark Bohr , Irwin Yablok
IPC分类号： H01L29/72
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66795 , H01L29/785 , H01L29/78687
摘要： A semiconductor transistor structure with increased mobility in the channel zone and a method of its fabrication are described. A semiconductor substrate having a first dopant is formed. A diffusion barrier layer having a second dopant is formed on the semiconductor substrate to suppress outdiffusion of the first dopant. Next, a semiconductor layer having substantially low dopant concentration relative to the first layer is epitaxially grown on the diffusion barrier layer. The semiconductor layer defines a channel in the semiconductor transistor structure. The low dopant concentration in the semiconductor layer increases the mobility of the carriers in the channel of the semiconductor transistor structure. A gate electrode and a gate dielectric are formed on the semiconductor layer with the low dopant concentration.
摘要翻译：描述了在沟道区中具有增加的迁移率的半导体晶体管结构及其制造方法。形成具有第一掺杂剂的半导体衬底。在半导体衬底上形成具有第二掺杂剂的扩散阻挡层，以抑制第一掺杂剂的扩散。接下来，在扩散阻挡层上外延生长相对于第一层具有相当低的掺杂剂浓度的半导体层。半导体层限定半导体晶体管结构中的沟道。半导体层中的低掺杂剂浓度增加了半导体晶体管结构的沟道中载流子的迁移率。在低掺杂浓度的半导体层上形成栅极电极和栅极电介质。

5. 发明授权

US07473614B2 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer 失效
公开(公告)号：US07473614B2
公开(公告)日：2009-01-06
申请号：US10987775
申请日：2004-11-12
申请人： Peter G. Tolchinsky , Martin D. Giles , Michael L. McSwiney , Mohamad Shaheen , Irwin Yablok
发明人： Peter G. Tolchinsky , Martin D. Giles , Michael L. McSwiney , Mohamad Shaheen , Irwin Yablok
IPC分类号： H01L21/76
CPC分类号： H01L21/26533 , H01L21/76243
摘要： Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

6. 发明授权

US06924543B2 Method for making a semiconductor device having increased carrier mobility 有权
标题翻译：制造具有增加的载流子迁移率的半导体器件的方法
公开(公告)号：US06924543B2
公开(公告)日：2005-08-02
申请号：US10463766
申请日：2003-06-16
申请人： Peter G. Tolchinsky , Irwin Yablok
发明人： Peter G. Tolchinsky , Irwin Yablok
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/72
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/823412 , H01L21/823481
摘要： A method and apparatus for a semiconductor device having increased electrical carrier mobility is described. That method and apparatus comprises forming two recesses within a substrate, and providing a material within the two recesses. The material has a predetermined coefficient of thermal expansion (CTE) to facilitate introduction of a predetermined strain within the substrate in a location between the two recesses. Also described is a semiconductor device that comprises a substrate having two recesses formed therein, and a material disposed within the two recesses. The material has a predetermined coefficient of thermal expansion (CTE) to facilitate introduction of a predetermined strain within the substrate in a location between the two recesses.
摘要翻译：描述了具有增加的电载流子迁移率的半导体器件的方法和装置。该方法和设备包括在基底内形成两个凹槽，并在两个凹槽内提供材料。该材料具有预定的热膨胀系数（CTE），以便于在两个凹部之间的位置中将衬底内的预定应变引入。还描述了一种半导体器件，其包括其中形成有两个凹部的衬底和设置在两个凹部内的材料。该材料具有预定的热膨胀系数（CTE），以便于在两个凹部之间的位置中将衬底内的预定应变引入。

7. 发明申请

US20100155880A1 Back gate doping for SOI substrates 审中-公开
标题翻译： SOI衬底的背栅掺杂
公开(公告)号：US20100155880A1
公开(公告)日：2010-06-24
申请号：US12317449
申请日：2008-12-23
申请人： Ibrahim Ban , Peter G. Tolchinsky , Irwin Yablok
发明人： Ibrahim Ban , Peter G. Tolchinsky , Irwin Yablok
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/7841 , H01L29/78648
摘要： A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×1017 cm−3, a nitrogen layer adjacent to the back gate region of the base silicon substrate, a BOX layer adjacent to the nitrogen layer, and a thin silicon device layer adjacent to the BOX layer, wherein the thin silicon device layer has a first dopant concentration that is less than 1×1017 cm−3. In some implementations, the thin silicon device layer has a first dopant concentration that is less than 1×1015 cm−3.
摘要翻译：绝缘体上硅（SOI）衬底包括具有背栅区的基硅衬底，其中所述背栅区具有大于1×1017cm-3的第一掺杂浓度，与所述背栅相邻的氮层基底硅衬底的区域，与氮层相邻的BOX层以及与BOX层相邻的薄硅器件层，其中所述薄硅器件层具有小于1×1017cm-3的第一掺杂剂浓度。在一些实施方案中，薄硅器件层具有小于1×1015cm-3的第一掺杂剂浓度。

8. 发明授权

US07531429B2 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices 有权
标题翻译：用于制造用于集成电路器件的超薄器件层的方法和装置
公开(公告)号：US07531429B2
公开(公告)日：2009-05-12
申请号：US11397412
申请日：2006-04-03
申请人： Peter Tolchinsky , Irwin Yablok , Chuan Hu , Richard D. Emery
发明人： Peter Tolchinsky , Irwin Yablok , Chuan Hu , Richard D. Emery
IPC分类号： H01L21/46 , H01L21/30 , H01L21/76 , H01L21/00 , H01L21/762
CPC分类号： H01L21/6835 , H01L21/3063 , H01L21/76254 , H01L23/367 , H01L24/81 , H01L2221/68359 , H01L2221/68368 , H01L2224/16 , H01L2224/73204 , H01L2224/81801 , H01L2924/01019 , H01L2924/14 , H01L2924/181 , Y10S438/96 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.
摘要翻译：本发明的实施例在多孔硅晶片上使用硅来制造厚度较薄的IC器件晶片。在器件制造之后，临时支撑件被结合到器件层。然后通过分离多孔硅层将最上层的硅层与硅衬底分离。然后去除多孔硅层和临时支撑物，并且完成包装。本发明的实施例提供了可靠的，低成本的方法和装置，用于生产较薄的IC器件晶片，以显着增加IC器件的器件层与散热片之间的热导率。在替代实施例中，分层硅衬底包括在多孔硅层上的绝缘体层和绝缘体层上的硅层。

9. 发明申请

US20080122042A1 APPLICATIONS OF POLYCRYSTALLINE WAFERS 审中-公开
标题翻译：多晶硅膜的应用
公开(公告)号：US20080122042A1
公开(公告)日：2008-05-29
申请号：US11563626
申请日：2006-11-27
申请人： Michael Goldstein , Irwin Yablok
发明人： Michael Goldstein , Irwin Yablok
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/187 , H01L21/302 , H01L21/823437
摘要： A wafer comprising polycrystalline silicon is used in various applications, including as a handling wafer, a test wafer, a dummy wafer, or as a substrate in a bonded die. Use of polycrystalline material instead of single-crystal may lower expenses.
摘要翻译：包括多晶硅的晶片用于各种应用中，包括作为处理晶片，测试晶片，虚设晶片或作为接合芯片中的基板。使用多晶材料代替单晶可能会降低成本。

10. 发明申请

US20060102988A1 Method for manufacturing a silicon-on-Insulator (SOI) wafer with an etch stop layer 失效
标题翻译：用于制造具有蚀刻停止层的绝缘体上硅（SOI）晶片的方法
公开(公告)号：US20060102988A1
公开(公告)日：2006-05-18
申请号：US10987775
申请日：2004-11-12
申请人： Peter Tolchinsky , Martin Giles , Michael McSwiney , Mohamad Shaheen , Irwin Yablok
发明人： Peter Tolchinsky , Martin Giles , Michael McSwiney , Mohamad Shaheen , Irwin Yablok
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/26533 , H01L21/76243
摘要： Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
摘要翻译：公开了具有覆盖掩埋氧化物层的蚀刻停止层的绝缘体上硅（SOI）晶片的实施例以及其制造方法的实施例。蚀刻停止层可以包括氮化硅，氮掺杂二氧化硅或氮氧化硅，以及这些材料的某些组合。描述和要求保护其他实施例。

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