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1. 发明授权

US5860149A Memory buffer system using a single pointer to reference multiple associated data 失效
标题翻译：内存缓冲系统使用单个指针来引用多个关联数据
公开(公告)号：US5860149A
公开(公告)日：1999-01-12
申请号：US484592
申请日：1995-06-07
申请人： Peter Fiacco , Wayne Rickard , Vi Chau
发明人： Peter Fiacco , Wayne Rickard , Vi Chau
IPC分类号： G06F13/00 , G06F5/06 , G06F12/02 , H04L13/08 , G06F12/06
CPC分类号： G06F5/06 , G06F12/023 , G06F2205/064
摘要： A partitioned memory is divided into a number of large buffers, and one or more of the large buffers is divided to create an equal number of small buffers. Each remaining large buffer is associated with one small buffer, and the paired buffers may be addressed by a single pointer. The pointers are stored in a first-in-first-out unit to create a pool of available buffer pairs.
摘要翻译：分区存储器被分成多个大缓冲器，并且一个或多个大缓冲器被分割以产生相等数量的小缓冲器。每个剩余的大缓冲区与一个小缓冲区相关联，并且配对缓冲区可以由单个指针寻址。指针存储在先进先出单元中，以创建可用缓冲区对。

2. 发明授权

US6041397A Efficient transmission buffer management system 有权
标题翻译：高效的传输缓冲管理系统
公开(公告)号：US6041397A
公开(公告)日：2000-03-21
申请号：US229464
申请日：1999-01-12
申请人： Wayne Rickard , Peter Fiacco , Vi Chau
发明人： Wayne Rickard , Peter Fiacco , Vi Chau
IPC分类号： G06F13/00 , G06F5/06 , G06F12/02 , H04L13/08 , G06F12/00
CPC分类号： G06F5/06 , G06F12/023 , G06F2205/064
摘要： A system is configured to provide an efficient management or control of a buffer memory system. The system can also be used to transmit data between communicating components of a computer system. A first-in-first-out memory stores a list of buffer pointers, and control logic returns buffer pointers from the transmit registers, and moves buffer pointers to the bottom of the FIFO memory.
摘要翻译：系统被配置为提供缓冲存储器系统的有效管理或控制。该系统还可用于在计算机系统的通信组件之间传输数据。先进先出的存储器存储缓冲器指针的列表，并且控制逻辑从发送寄存器返回缓冲器指针，并将缓冲器指针移动到FIFO存储器的底部。

3. 发明授权

US5745727A Linked caches memory for storing units of information 失效
标题翻译：链接缓存用于存储信息单元的存储器
公开(公告)号：US5745727A
公开(公告)日：1998-04-28
申请号：US843315
申请日：1997-04-15
申请人： Vi Chau , Stuart Berman , Peter Fiacco
发明人： Vi Chau , Stuart Berman , Peter Fiacco
IPC分类号： G06F13/00 , G06F12/00 , G06F12/08 , H04L12/56
CPC分类号： G06F12/0897
摘要： A method and apparatus for linking two independent caches which have related information stored therein. Each unit of information stored in a first cache memory is associated with one unit of information stored in the second cache memory. Each unit of information stored in the first cache memory includes a pointer or index to the associated information unit in the second cache memory. Each information unit stored in the second cache is only stored once, regardless of the number of units in the first cache that are associated with a particular unit within the second cache. Therefore, even if more than one unit of information within the first cache memory is associated with the same unit of information within the second cache memory, that unit of information stored in the second cache memory is only stored once.
摘要翻译：一种用于链接具有存储在其中的相关信息的两个独立高速缓存的方法和装置。存储在第一高速缓冲存储器中的每个信息单元与存储在第二高速缓冲存储器中的一个信息单元相关联。存储在第一高速缓冲存储器中的每个信息单元包括指向第二高速缓冲存储器中的关联信息单元的指针或索引。存储在第二高速缓存中的每个信息单元仅存储一次，而与第二高速缓存中的特定单元相关联的第一高速缓存中的单元数量无关。因此，即使第一高速缓冲存储器内的多于一个信息单元与第二高速缓冲存储器内的相同信息单元相关联，也只存储存储在第二高速缓冲存储器中的信息单元一次。

4. 发明授权

US5659720A Computer control device for managing a timer array 失效
标题翻译：用于管理定时器阵列的计算机控制装置
公开(公告)号：US5659720A
公开(公告)日：1997-08-19
申请号：US429916
申请日：1995-04-27
申请人： Peter Fiacco , Vi Chau , Jennifer Sullivan
发明人： Peter Fiacco , Vi Chau , Jennifer Sullivan
IPC分类号： G06F1/14 , G06F11/00 , G06F11/34
CPC分类号： G06F11/0757 , G06F1/14 , G06F11/3466
摘要： A method and apparatus for establishing a large number of EDTOV timers, each determining when an event has failed to occur on an exchange of a communications protocol. Values for each timer are maintained as a timer array. The entire timer array is read at regular scan intervals by a state machine and decremented by four associated hardware decrementers, four timers at one time. A Scan Interval variable determines the scan interval. The present invention is capable of scan intervals of up to 100 ns. Active time values are read, checked for zero, decremented preferably by one, and written back to the timer array. If a timer is detected as having timed out (equal to zero), then a value which identifies the exchange associated with that timer is logged into a time-out FIFO and "FF"h is written back into the timer. At the heart of the invention is the efficient use of dedicated hardware to decrement or otherwise alter the values of each timer as appropriate, and the use of a dedicated state machine to read values for each timer, provide the value to the hardware, and then load the new value of each timer back into memory.
摘要翻译：一种用于建立大量EDTOV定时器的方法和装置，每个定时器确定事件何时在通信协议的交换上发生。每个定时器的值被保持为定时器阵列。整个定时器阵列由状态机以规则的扫描间隔读取，并由四个关联的硬件递减器一次递减四个定时器。扫描间隔变量确定扫描间隔。本发明能够进行高达100ns的扫描间隔。活动时间值被读取，检查为零，最好递减1，并写回定时器阵列。如果检测到定时器具有超时（等于零），则将与该定时器相关联的交换的值记录到超时FIFO中，并将“FF”h写回定时器。本发明的核心在于适当地有效利用专用硬件来递减或以其他方式改变每个定时器的值，并且使用专用状态机来读取每个定时器的值，为硬件提供值，然后将每个定时器的新值加载到内存中。

5. 发明授权

US6005849A Full-duplex communication processor which can be used for fibre channel frames 失效
标题翻译：全双工通信处理器，可用于光纤通道帧
公开(公告)号：US6005849A
公开(公告)日：1999-12-21
申请号：US937066
申请日：1997-09-24
申请人： Bradley Roach , Peter Fiacco , Greg Scherer
发明人： Bradley Roach , Peter Fiacco , Greg Scherer
IPC分类号： G06F13/10 , G06F13/12 , H04L12/28 , H04L12/56 , H04L29/06 , H04L29/10 , H04B1/56 , H04L5/14
CPC分类号： H04L49/901 , G06F13/124 , H04L12/2801 , H04L29/06 , H04L49/90 , H04L49/9089 , H04L69/12
摘要： A full duplex communication processor simultaneously sends and receives frames of data and commands. Separate transmit and receive protocol engines are controlled by separate sequencers. This enables frames of data to be received and transmitted simultaneously without involving a host CPU on a frame-by-frame basis.
摘要翻译：全双工通信处理器同时发送和接收数据帧和数据帧。单独的发送和接收协议引擎由独立的定序器控制。这使得数据帧能够同时接收和传输，而不需要逐帧地涉及主机CPU。

6. 发明授权

US06829660B2 Supercharge message exchanger 有权
标题翻译：增压消息交换机
公开(公告)号：US06829660B2
公开(公告)日：2004-12-07
申请号：US10316604
申请日：2002-12-10
申请人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
发明人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
IPC分类号： G06F1328
CPC分类号： G06F13/28 , G06F13/387
摘要： A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
摘要翻译：具有第一随机存取存储器（RAM），第二RAM，耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。第一个RAM被配置为存储来自至少两个引擎的输入/输出（I / O）完成。第二RAM还被配置为存储来自至少两个引擎的I / O完成。当所有引擎都处于活动状态时，系统将I / O完成从引擎写入第一个和第二个RAM。第一个处理器处理存储在第一个RAM中的I / O完成。第二处理器处理存储在第二RAM中的I / O完成。

7. 发明授权

US06304910B1 Communication processor having buffer list modifier control bits 失效
标题翻译：具有缓冲器列表修改器控制位的通信处理器
公开(公告)号：US06304910B1
公开(公告)日：2001-10-16
申请号：US08937065
申请日：1997-09-24
申请人： Bradley Roach , Peter Fiacco , Greg Scherer , Stuart Berman , David Duckman
发明人： Bradley Roach , Peter Fiacco , Greg Scherer , Stuart Berman , David Duckman
IPC分类号： G06F1300
CPC分类号： H04L49/9089 , H04L29/06 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9052 , H04L49/9094 , H04L69/12
摘要： A communication processor sends and receives frames of data and commands. Transmit and receive protocol engine is controlled by host driver software which utilizes predetermined bits to indicate which frame is the last frame in a series of frames. This information is then placed in the transmit frame before it is sent.
摘要翻译：通信处理器发送和接收数据帧和数据帧。发送和接收协议引擎由主机驱动程序软件控制，主机驱动程序使用预定位来指示哪一帧是一系列帧中的最后一帧。然后将该信息发送到发送帧之前。

8. 发明授权

US6098125A Method of mapping fibre channel frames based on control and type header fields 失效
标题翻译：基于控制和类型头字段映射光纤通道帧的方法
公开(公告)号：US6098125A
公开(公告)日：2000-08-01
申请号：US71276
申请日：1998-05-01
申请人： Peter Fiacco , Bradley Roach , Karl M. Henson
发明人： Peter Fiacco , Bradley Roach , Karl M. Henson
IPC分类号： G06F13/14 , H04L12/56 , G06F13/00
CPC分类号： H04L47/6215 , H04L47/2441 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9042 , H04L49/9047
摘要： A method and apparatus for processing and transferring frames of data in a computer data link that maps incoming frames to a specific buffer ring in host memory based on routing control and type fields in each frame. More particularly, a Fibre Channel link port contains receiver routing code (RRCode) registers that allow host software to set up routing control (R.sub.-- CTL) match and mask fields, and TYPE match and mask fields. The link port uses these registers to match and mask against corresponding R.sub.-- CTL/TYPE fields in a received frame to determine which of several R.sub.-- CTL/TYPE host memory buffer rings should be used to store the received frame. The link port places a code (RRCode) in a start of frame (SOF) status word associated with a frame. The RRCode indicates a specific R.sub.-- CTL/TYPE host memory buffer ring, or indicates that no match was found or that multiple matches were found. A protocol engine reads the RRCode field in the SOF status word of the received frame, and queues a direct memory access (DMA) operation to an appropriate R.sub.-- CTL/TYPE buffer ring. The host may then process the contents of the indicated buffer ring. Since the buffer rings are "pre-sorted" as to frame type, the host may more efficiently respond to incoming frames.
摘要翻译：一种在计算机数据链路中处理和传送数据帧的方法和装置，该计算机数据链路基于每个帧中的路由控制和类型字段将输入帧映射到主机存储器中的特定缓冲环。更具体地，光纤通道链路端口包含允许主机软件建立路由控制（R-CTL）匹配和掩码字段以及TYPE匹配和掩码字段的接收机路由代码（RRCode）寄存器。链路端口使用这些寄存器来匹配和掩蔽接收到的帧中的相应的R-CTL / TYPE字段，以确定应该使用几个R-CTL / TYPE主机内存缓冲区中的哪一个来存储接收到的帧。链路端口将代码（RRCode）放置在与帧相关联的帧（SOF）状态字的起始处。 RRCode指示特定的R-CTL / TYPE主机内存缓冲区环，或表示未找到匹配或找到多个匹配。协议引擎读取接收到的帧的SOF状态字中的RRCode字段，并将直接存储器访问（DMA）操作排队到适当的R-CTL / TYPE缓冲环。然后，主机可以处理指示的缓冲环的内容。由于缓冲环针对帧类型进行“预排序”，所以主机可以更有效地响应输入帧。

9. 发明授权

US07363396B2 Supercharge message exchanger 有权
标题翻译：增压消息交换机
公开(公告)号：US07363396B2
公开(公告)日：2008-04-22
申请号：US11361344
申请日：2006-02-24
申请人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
发明人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
IPC分类号： G06F13/12 , G06F3/00 , G06F13/28
CPC分类号： G06F13/28 , G06F13/387
摘要： A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
摘要翻译：具有第一随机存取存储器（RAM），第二RAM，耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。第一个RAM被配置为存储来自至少两个引擎的输入/输出（I / O）完成。第二RAM还被配置为存储来自至少两个引擎的I / O完成。当所有引擎都处于活动状态时，系统将I / O完成从引擎写入第一个和第二个RAM。第一个处理器处理存储在第一个RAM中的I / O完成。第二处理器处理存储在第二RAM中的I / O完成。

10. 发明授权

US07096296B2 Supercharge message exchanger 失效
公开(公告)号：US07096296B2
公开(公告)日：2006-08-22
申请号：US10995456
申请日：2004-11-22
申请人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
发明人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
IPC分类号： G06F13/24 , G06F13/32
CPC分类号： G06F13/28 , G06F13/387
摘要： A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

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