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1. 发明授权

US06405271B1 Data flow control mechanism for a bus supporting two-and three-agent transactions 失效
标题翻译：支持二代理和三代理交易的总线数据流控制机制
公开(公告)号：US06405271B1
公开(公告)日：2002-06-11
申请号：US08709215
申请日：1996-09-06
申请人： Peter D. MacWilliams , Nitin V. Sarangdhar , Stephen S. Pawlowski , Gurbir Singh
发明人： Peter D. MacWilliams , Nitin V. Sarangdhar , Stephen S. Pawlowski , Gurbir Singh
IPC分类号： G06F1300
CPC分类号： G06F13/368 , G06F13/36 , G06F13/37 , G06F13/4213
摘要： A data flow control mechanism for a bus supporting two- and three-agent transactions includes a control logic to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has received an indication from another agent coupled to the bus that the other agent is ready to receive the data.
摘要翻译：支持二代理和三代理交易的总线的数据流控制机制包括一个将请求的指示置于计算机系统总线上的控制逻辑。在总线上放置指示的代理然后等待将与该请求相对应的数据放置在总线上，直到其接收到来自耦合到总线的另一代理程序的指示，即其他代理程序准备好接收数据。

2. 发明授权

US06253302B1 Method and apparatus for supporting multiple overlapping address spaces on a shared bus 失效
公开(公告)号：US06253302B1
公开(公告)日：2001-06-26
申请号：US08705684
申请日：1996-08-29
申请人： Peter D. MacWilliams , Stephen S. Pawlowski
发明人： Peter D. MacWilliams , Stephen S. Pawlowski
IPC分类号： G06F1200
CPC分类号： G06F11/1016 , G06F12/0623
摘要： A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

3. 再颁专利

USRE38388E1 Method and apparatus for performing deferred transactions 有权
标题翻译：执行延期交易的方法和装置
公开(公告)号：USRE38388E1
公开(公告)日：2004-01-13
申请号：US09882444
申请日：2001-06-14
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： H04L12417
CPC分类号： G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

4. 发明授权

US5923857A Method and apparatus for ordering writeback data transfers on a bus 失效
标题翻译：在总线上订购回写数据传输的方法和装置
公开(公告)号：US5923857A
公开(公告)日：1999-07-13
申请号：US708922
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
IPC分类号： G06F12/08 , G06F13/14 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to ensure that a first portion which includes the critical portion of the data is transferred to the bus first.
摘要翻译：用于排序数据传输的方法和装置包括从请求代理接收的数据的关键部分的标识符以及数据请求。然后将与所请求的数据相对应的回写数据作为多个部分传送到总线，并被排序以确保包括数据的关键部分的第一部分首先被传送到总线。

5. 发明授权

US5919254A Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system 失效
标题翻译：用于在多处理系统中切换源同步和公共时钟数据传输模式的方法和装置
公开(公告)号：US5919254A
公开(公告)日：1999-07-06
申请号：US881941
申请日：1997-06-25
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , William S. Wu , Len J. Schultz
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , William S. Wu , Len J. Schultz
IPC分类号： G06F13/38 , G06F13/40 , G06F1/12 , G06F13/42
CPC分类号： G06F13/385 , G06F13/4018 , G06F13/405
摘要： A method and apparatus for transferring data between bus agents in a computer system including a bus operating at a bus clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transaction request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.
摘要翻译：一种用于在包括以总线时钟速率工作的总线的计算机系统中的总线代理之间传送数据的方法和装置。该方法包括从请求代理接收交易请求的步骤，包括请求代理处理的多个数据宽度的指示。响应于交易请求，根据请求代理和响应代理进程的数据宽度配置数据传输。如果数据宽度是第一多个数据宽度之一，则相对于总线时钟异步执行数据传输，否则，数据传输是相对于总线时钟同步执行的。

6. 发明授权

US5911053A Method and apparatus for changing data transfer widths in a computer system 失效
标题翻译：用于在计算机系统中改变数据传输宽度的方法和装置
公开(公告)号：US5911053A
公开(公告)日：1999-06-08
申请号：US723572
申请日：1996-09-30
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Gurbir Singh
IPC分类号： G06F13/40 , G06F3/00
CPC分类号： G06F13/4018
摘要： In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.
摘要翻译：在用于改变计算机系统中的数据传输宽度的方法和装置中，总线上的第一代理向总线上的第二代理提供第一指示，以识别第一代理所支持的一个或多个数据传输宽度。然后，第二代理向第一代理提供识别由第二代理支持的一个或多个数据传输宽度的第二指示。然后基于第一指示和第二指示确定数据传输宽度。根据本发明的实施例，参与交易的第三代理还能够向第一代理和/或第二代理提供第三指示，以识别由第三代理支持的一个或多个数据传输宽度。然后基于第一，第二和第三指示确定数据传送宽度。

7. 发明授权

US5796977A Highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构
公开(公告)号：US5796977A
公开(公告)日：1998-08-18
申请号：US688238
申请日：1996-07-29
申请人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
IPC分类号： G06F12/08 , G06F13/18 , G06F12/00 , G06F13/00
CPC分类号： G06F13/18 , G06F12/0831
摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
摘要翻译：描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

8. 发明授权

US5996042A Scalable, high bandwidth multicard memory system utilizing a single memory controller 失效
标题翻译：可扩展的，高带宽的多卡存储系统利用单个存储器控制器
公开(公告)号：US5996042A
公开(公告)日：1999-11-30
申请号：US766955
申请日：1996-12-16
申请人： Stephen S. Pawlowski , Peter D. MacWilliams
发明人： Stephen S. Pawlowski , Peter D. MacWilliams
IPC分类号： G06F13/16
CPC分类号： G06F13/1668
摘要： A high speed memory interface for a processor-based computing system provides a bridge component (made up of a controller and a data path), one or more data multiplexer/buffers, and a plurality of RAS/CAS generators. The high speed memory interface allows for the expansion of the memory subsystem without additional loading on the processor/system bus and without a reduction in memory transaction performance. The interface includes a single controller for receiving memory transaction commands from the processor/system bus, and a plurality of RAS/CAS generators, for generating RAS/CAS signals in response to memory transaction commands forwarded by the controller. Each RAS/CAS generator is coupled to one or more memory banks. A data multiplexer/buffer is coupled to one or more of the memory banks, and provides an interface between the memory bank(s) and the data path.
摘要翻译：用于基于处理器的计算系统的高速存储器接口提供由组件（由控制器和数据路径组成），一个或多个数据多路复用器/缓冲器以及多个RAS / CAS发生器。高速存储器接口允许存储器子系统的扩展，而不需要在处理器/系统总线上进行额外的负载，而不会降低存储器事务性能。接口包括用于从处理器/系统总线接收存储器事务命令的单个控制器和用于响应于由控制器转发的存储器事务命令来生成RAS / CAS信号的多个RAS / CAS发生器。每个RAS / CAS发生器耦合到一个或多个存储体。数据多路复用器/缓冲器耦合到一个或多个存储体，并且提供存储体和数据通路之间的接口。

9. 发明授权

US5905876A Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system 失效
标题翻译：多并发事务计算机系统中的内存和I / O事务的队列排序
公开(公告)号：US5905876A
公开(公告)日：1999-05-18
申请号：US766954
申请日：1996-12-16
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , D. Michael Bell
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , D. Michael Bell
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F13/1642 , G06F12/0835
摘要： A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.
摘要翻译：用于基于处理器的计算系统的事务排序机制确保处理器，I / O和存储器子系统之间的事务的正确排序，确保计算系统内的高速缓存一致性，并且有助于并发交易，从而实现高带宽，免费操作。存储器事务的I / O和处理器到存储器事务按照这种事务在处理器总线上出现的顺序被放置在存储器请求队列中; 存储器事务的I / O按照这种事务出现在I / O总线上的顺序放置在入站请求队列中; 并且处理器到I / O事务和对应于分割事务I / O到存储器读取事务的完成被放置在出站请求队列中，其中分割事务I / O到存储器读取事务和处理器到I / O事务出现在处理器总线上。

10. 发明授权

US5903916A Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation 失效
标题翻译：用于在读取或刷新操作期间的访问等待时间期间执行机会性写入数据传输的计算机存储器子系统和方法
公开(公告)号：US5903916A
公开(公告)日：1999-05-11
申请号：US766950
申请日：1996-12-16
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Sridhar Lakshmanamurthy
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Sridhar Lakshmanamurthy
IPC分类号： G06F13/16 , G11C7/10 , G11C7/22 , G06F13/00 , G11C11/407
CPC分类号： G06F13/1626 , G11C7/1072 , G11C7/22
摘要： A computer memory subsystem and associated method are disclosed in which memory transaction latency and bandwidth in the memory subsystem are improved through the opportunistic transfer of write data from a data path to a memory buffer coupled to a targeted memory bank during an access latency period within a non-memory write operation, such as, e.g., a read or refresh operation. The opportunistic write data transfer operation utilizes otherwise unused memory data bus cycles within a read or refresh operation for performance of the write data transfer, without adding clock cycles to the read or refresh operation. Because the write data is transferred to the memory buffer coupled to the memory bank during the latency period of the memory operation preceding the write operation, the total turnaround time for, e.g., performing a read operation followed by a write operation is reduced.
摘要翻译：公开了一种计算机存储器子系统和相关联的方法，其中通过在写入数据从数据路径到连接到目标存储体的存储缓冲器的机会性传输期间，在存储器子系统内的存储器事务等待时间和带宽在非存储器写入操作，例如读取或刷新操作。机会性写入数据传输操作利用在读取或刷新操作期间的未使用的存储器数据总线周期来执行写入数据传输，而不向读取或刷新操作添加时钟周期。由于在写入操作之前的存储器操作的等待时段期间，将写入数据传送到耦合到存储体的存储器缓冲器，所以例如执行读取操作之后进行写入操作的总周转时间减少。

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