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1. 发明授权

US5618756A Selective WSix deposition 失效
标题翻译：选择性WSix沉积
公开(公告)号：US5618756A
公开(公告)日：1997-04-08
申请号：US639391
申请日：1996-04-29
申请人： Peter Chew , Chuck Jang
发明人： Peter Chew , Chuck Jang
IPC分类号： H01L21/285 , H01L21/768 , H01L21/312 , H01L21/44
CPC分类号： H01L21/76879 , H01L21/28518
摘要： A method for selectively depositing WSi.sub.x is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein WSi.sub.x is to be deposited overlying a first portion of the substrate and wherein WSi.sub.x is not to be deposited overlying a second portion of the substrate. A layer of organic material is provided over the surface of the substrate overlying the second portion of the substrate. A layer of WSi.sub.x is deposited over the surface of the substrate wherein the WSi.sub.x is deposited overlying the first portion of the substrate and wherein the presence of the organic material layer prevents the WSi.sub.x from depositing overlying the second portion of the substrate completing the selective WSi.sub.x deposition in the fabrication of an integrated circuit device.
摘要翻译：描述了一种用于选择性地放置WSix的方法。半导体器件结构设置在半导体衬底中和之上，其中WSix将被沉积在衬底的第一部分上，并且其中WSix不被沉积覆盖在衬底的第二部分上。在衬底的覆盖衬底的第二部分的表面上方提供一层有机材料。一层WSix沉积在衬底的表面上，其中WSix沉积在衬底的第一部分上，并且其中有机材料层的存在防止WSix沉积覆盖衬底的第二部分，从而完成选择性WSix沉积在制造集成电路器件时。

2. 发明授权

US06258676B1 Method for forming a shallow trench isolation using HDP silicon oxynitride 失效
标题翻译：使用HDP氮氧化硅形成浅沟槽隔离的方法
公开(公告)号：US06258676B1
公开(公告)日：2001-07-10
申请号：US09431241
申请日：1999-11-01
申请人： Kong Hean Lee , Peter Chew
发明人： Kong Hean Lee , Peter Chew
IPC分类号： H01L21336
CPC分类号： H01L21/76232
摘要： A Method for forming a shallow trench isolation using HDP silicon oxynitride. A pad oxide layer is formed on a semiconductor substrate having an active area and an isolation area and a barc layer is formed over the pad oxide layer. The barc layer, the pad oxide layer, and the semiconductor substrate are patterned to form a trench having rounded corners in the isolation area. A liner oxide layer is formed over the semiconductor substrate, and a gap fill layer is formed on the liner oxide layer. An important feature of the invention is that the gap fill layer is composed of silicon oxynitride formed using a high density plasma chemical vapor deposition process. A portion of the gap fill layer over the active area can be removed using a reverse trench mask etch, and the gap fill layer is further planarized with a chemical mechanical polishing process using the liner oxide layer as chemical mechanical polishing stop.
摘要翻译：使用HDP氮氧化硅形成浅沟槽隔离的方法。在具有有源区和隔离区的半导体衬底上形成衬垫氧化物层，并且在衬垫氧化物层上形成棒状层。图案化条形层，衬垫氧化物层和半导体衬底，以在隔离区域中形成具有圆角的沟槽。衬底氧化物层形成在半导体衬底之上，衬垫氧化物层上形成间隙填充层。本发明的一个重要特征是间隙填充层由使用高密度等离子体化学气相沉积工艺形成的氧氮化硅组成。可以使用反向沟槽掩模蚀刻去除有源区域上的间隙填充层的一部分，并且使用衬垫氧化物层作为化学机械抛光停止，通过化学机械抛光工艺进一步平坦化间隙填充层。

3. 发明授权

US06383922B1 Thermal stability improvement of CoSi2 film by stuffing in titanium 失效
标题翻译： CoSi2薄膜通过填充钛的热稳定性提高
公开(公告)号：US06383922B1
公开(公告)日：2002-05-07
申请号：US09872558
申请日：2001-06-04
申请人： Bei Chao Zhang , Chung Woh Lai , Eng Hua Lim , Mei Sheng Zhou , Peter Chew , Arthur Ang
发明人： Bei Chao Zhang , Chung Woh Lai , Eng Hua Lim , Mei Sheng Zhou , Peter Chew , Arthur Ang
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L29/4933
摘要： A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. The titanium layer provides titanium atoms which diffuse into the cobalt disilicide thereby increasing its thermal stability. The titanium layer is removed to complete formation of a thermally stable cobalt disilicide film in the manufacture of an integrated circuit.
摘要翻译：描述了在制造集成电路中形成热稳定性二硅化二硅膜的方法。提供具有要被硅化的硅区域的半导体衬底。覆盖待硅化硅的区域上沉积钴层。覆盖在钴层上的覆盖层。对衬底进行第一快速热退火，由此将钴转化为单硅硅酸盐，其中它覆盖在硅区域上，并且其中不覆盖硅区域的钴是未反应的。去除未反应的钴层和覆盖层。沉积在一氧化硅钴层上的钛层。此后，将衬底进行第二次快速热退火，由此使一价硅酸钴转化为二硅化钴。钛层提供扩散到二硅化钴中的钛原子，从而增加其热稳定性。去除钛层以在制造集成电路中完成热稳定的二硅化硅膜的形成。

4. 发明授权

US06528886B2 Intermetal dielectric layer for integrated circuits 有权
标题翻译：用于集成电路的金属间电介质层
公开(公告)号：US06528886B2
公开(公告)日：2003-03-04
申请号：US10135330
申请日：2002-04-29
申请人： Huang Liu , John Sudijono , Juan Boon Tan , Edwin Goh , Alan Cuthbertson , Arthur Ang , Feng Chen , Qiong Li , Peter Chew
发明人： Huang Liu , John Sudijono , Juan Boon Tan , Edwin Goh , Alan Cuthbertson , Arthur Ang , Feng Chen , Qiong Li , Peter Chew
IPC分类号： H01L2348
CPC分类号： H01L21/76826 , H01L21/31612 , H01L21/31629 , H01L21/76831
摘要： An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
摘要翻译：提供了一种用于集成电路的金属间电介质结构，其上具有前金属电介质和金属线，在前金属介电层和金属线上具有SRO衬垫，在SRO衬垫上的FGS电介质层，在FGS介电层上的SRO膜，以及SRO膜上的TEOS电介质层。通过FGS介电层的通孔被处理成在通孔周围具有无氟区域。该结构不会对金属线或通孔发生氟侵蚀，同时具有较少氟排出和扩散的稳定的FGS介电层。

5. 发明申请

US20080029853A1 INTEGRATED CIRCUIT SYSTEM WITH CONTACT FILM 有权
标题翻译：具有接触膜的集成电路系统
公开(公告)号：US20080029853A1
公开(公告)日：2008-02-07
申请号：US11462036
申请日：2006-08-02
申请人： Chih Ping Yong , Peter Chew , Chuin Boon Yeap , Hoon Lian Yap , Ranbir Singh , Nace Rossi , Jovin Lim
发明人： Chih Ping Yong , Peter Chew , Chuin Boon Yeap , Hoon Lian Yap , Ranbir Singh , Nace Rossi , Jovin Lim
IPC分类号： H01L23/58
CPC分类号： H01L21/76801 , H01L21/76804 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.
摘要翻译：一种集成电路系统，包括提供集成电路器件，在所述集成电路器件上形成未掺杂绝缘层，在所述未掺杂绝缘层上形成薄绝缘层，在所述薄绝缘层上形成掺杂绝缘层，以及在所述绝缘层上形成接触未掺杂的绝缘层，薄绝缘层和掺杂绝缘层。

6. 发明授权

US06451687B1 Intermetal dielectric layer for integrated circuits 有权
公开(公告)号：US06451687B1
公开(公告)日：2002-09-17
申请号：US09721898
申请日：2000-11-24
申请人： Huang Liu , John Sudijono , Juan Boon Tan , Edwin Goh , Alan Cuthbertson , Arthur Ang , Feng Chen , Qiong Li , Peter Chew
发明人： Huang Liu , John Sudijono , Juan Boon Tan , Edwin Goh , Alan Cuthbertson , Arthur Ang , Feng Chen , Qiong Li , Peter Chew
IPC分类号： H01L214763
CPC分类号： H01L21/76826 , H01L21/31612 , H01L21/31629 , H01L21/76831
摘要： An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

7. 发明授权

US08685861B2 Integrated circuit system with contact distribution film 有权
标题翻译：具有接触分布膜的集成电路系统
公开(公告)号：US08685861B2
公开(公告)日：2014-04-01
申请号：US11462036
申请日：2006-08-02
申请人： Chih Ping Yong , Peter Chew , Chuin Boon Yeap , Hoon Lian Yap , Ranbir Singh , Nace Rossi , Jovin Lim
发明人： Chih Ping Yong , Peter Chew , Chuin Boon Yeap , Hoon Lian Yap , Ranbir Singh , Nace Rossi , Jovin Lim
IPC分类号： H01L21/311
CPC分类号： H01L21/76801 , H01L21/76804 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.
摘要翻译：一种集成电路系统，包括提供集成电路器件，在所述集成电路器件上形成未掺杂绝缘层，在所述未掺杂绝缘层上形成薄绝缘层，在所述薄绝缘层上形成掺杂绝缘层，以及在所述绝缘层上形成接触未掺杂的绝缘层，薄绝缘层和掺杂绝缘层。

8. 发明授权

US5858876A Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer 失效
标题翻译：用于在图案化衬底层上形成无空隙和间隙填充绝缘体层的同时沉积和蚀刻方法
公开(公告)号：US5858876A
公开(公告)日：1999-01-12
申请号：US617701
申请日：1996-04-01
申请人： Peter Chew
发明人： Peter Chew
IPC分类号： H01L21/316 , H01L21/768 , H01L21/02
CPC分类号： H01L21/316 , H01L21/76819
摘要： A method for forming a void-free and gap-filling doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit. Formed upon a semiconductor substrate is a patterned substrate layer. Formed upon the patterned substrate layer is a doped silicon oxide insulator layer. The doped silicon oxide insulator layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method. The Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employ a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.
摘要翻译：一种用于在集成电路内的图案化衬底层上形成无空隙和填充间隙的氧化硅绝缘体层的方法。在半导体衬底上形成图案化衬底层。在图案化的衬底层上形成掺杂的氧化硅绝缘体层。掺杂的氧化硅绝缘体层通过等离子体增强化学气相沉积（PECVD）沉积方法形成，该沉积方法与反应离子蚀刻（RIE）回蚀法同时进行。等离子体增强化学气相沉积（PECVD）沉积方法和反应离子蚀刻（RIE）回蚀法同时使用四乙基硅酸钠（TEOS）硅源材料，掺杂剂源材料，氧源材料和蚀刻气体。

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