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1. 发明授权

US07231562B2 Memory module, test system and method for testing one or a plurality of memory modules 有权
标题翻译：用于测试一个或多个存储器模块的存储器模块，测试系统和方法
公开(公告)号：US07231562B2
公开(公告)日：2007-06-12
申请号：US10754455
申请日：2004-01-09
申请人： Carsten Ohlhoff , Peter Beer
发明人： Carsten Ohlhoff , Peter Beer
IPC分类号： G01R31/28
CPC分类号： G11C29/40 , G11C2029/0405 , G11C2029/1208 , G11C2029/2602
摘要： The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.
摘要翻译：本发明涉及一种具有存储器单元和自检电路的集成存储器模块，该自检电路以这样一种方式实现：提供用于测试存储器单元中的存储器区域的测试数据和测试地址，并产生缺陷数据取决于缺陷的检测，提供测试电路以便从要被检测的一个或多个可连接存储器模块接收缺陷数据，该测试电路被配置成存储接收的缺陷数据取决于在存储器单元中分配给其的地址。

2. 发明授权

US07137049B2 Method and apparatus for masking known fails during memory tests readouts 有权
公开(公告)号：US07137049B2
公开(公告)日：2006-11-14
申请号：US10425224
申请日：2003-04-29
申请人： Jochen Hoffmann , Carsten Ohlhoff , Peter Beer
发明人： Jochen Hoffmann , Carsten Ohlhoff , Peter Beer
IPC分类号： G11C29/00
CPC分类号： G11C29/24
摘要： Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse. By masking the test results for memory elements (normal and redundant) that have been previously found defective, the memory elements may be tested in the same manner during front-end and back-end testing.

3. 发明授权

US06891431B2 Integrated semiconductor circuit configuration 失效
标题翻译：集成半导体电路配置
公开(公告)号：US06891431B2
公开(公告)日：2005-05-10
申请号：US10675761
申请日：2003-09-30
申请人： Peter Beer , Carsten Ohlhoff
发明人： Peter Beer , Carsten Ohlhoff
IPC分类号： G01R15/20 , G01R19/00 , H03F15/00 , G01R31/26
CPC分类号： G01R15/202 , G01R19/0092
摘要： To measure the current consumption of a circuit device with a current measuring device, the circuit device being supplied by a current/voltage supply line device, as simply as possible without the need for additional measuring devices, an integrated circuit configuration includes integrating the circuit configuration, the current measuring device, and, also, the current/voltage supply line device in a common chip and forming the current measuring device with a Hall sensor device.
摘要翻译：为了测量具有电流测量装置的电路装置的电流消耗，电路装置由电流/电压供应线装置提供，尽可能简单地不需要额外的测量装置，集成电路配置包括集成电路配置电流测量装置，以及公共芯片中的电流/电压供应线装置，并用霍尔传感器装置形成电流测量装置。

4. 发明授权

US07490274B2 Method and apparatus for masking known fails during memory tests readouts 失效
标题翻译：用于屏蔽的方法和装置在存储器测试读出期间失败
公开(公告)号：US07490274B2
公开(公告)日：2009-02-10
申请号：US11397790
申请日：2006-04-04
申请人： Jochen Hoffmann , Carsten Ohlhoff , Peter Beer
发明人： Jochen Hoffmann , Carsten Ohlhoff , Peter Beer
IPC分类号： G11C29/00
CPC分类号： G11C29/24
摘要： Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse. By masking the test results for memory elements (normal and redundant) that have been previously found defective, the memory elements may be tested in the same manner during front-end and back-end testing.
摘要翻译：本发明的实施例通常提供用于测试具有正常存储元件和冗余存储器元件的存储器件的方法和装置。在前端测试过程中，发现有缺陷的正常存储器元件被冗余存储元件代替。在前端测试期间，发现有缺陷的冗余存储器元件可能通过吹制相关的掩模保险丝而被标记为有缺陷的。在后端测试过程中，如果普通存储器元件已被冗余存储器元件代替，则测试正常存储器元件的结果可能会被屏蔽（例如，强制转换为传递结果）。类似地，如果冗余存储器元件先前被发现是有缺陷的，则由冗余存储元件测试的结果可以被掩蔽，如相关标记熔丝所示。通过掩盖以前发现有缺陷的存储器元件（正常和冗余）的测试结果，可以在前端和后端测试中以相同的方式测试存储器元件。

5. 发明授权

US07197678B2 Test circuit and method for testing an integrated memory circuit 有权
标题翻译：用于测试集成存储器电路的测试电路和方法
公开(公告)号：US07197678B2
公开(公告)日：2007-03-27
申请号：US10613367
申请日：2003-07-03
申请人： Carsten Ohlhoff , Peter Beer
发明人： Carsten Ohlhoff , Peter Beer
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/1201 , G11C11/401 , G11C29/40
摘要： A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit for comparing the test data written into the memory circuit with the test data read from the memory area. The data input line is connected to the memory circuit via a data change circuit. The data change circuit is controllable depending on a result of a comparison in the comparator unit such that when an error occurs, subsequent test data can be written in an altered manner to the memory circuit.
摘要翻译：用于测试存储器电路的测试电路具有用于提供测试数据的数据输入线和比较器单元。比较器单元连接到数据输入线和存储器电路，用于将写入存储器电路的测试数据与从存储区读取的测试数据进行比较。数据输入线通过数据变换电路连接到存储电路。根据比较器单元中的比较结果，数据变换电路是可控的，使得当发生错误时，后续测试数据可以以改变的方式写入存储器电路。

6. 发明授权

US06756787B2 Integrated circuit having a current measuring unit 失效
标题翻译：具有电流测量单元的集成电路
公开(公告)号：US06756787B2
公开(公告)日：2004-06-29
申请号：US10243067
申请日：2002-09-13
申请人： Carsten Ohlhoff , Peter Beer
发明人： Carsten Ohlhoff , Peter Beer
IPC分类号： H01H3102
CPC分类号： G01R31/3004 , G01R31/31924
摘要： The invention relates to an integrated circuit having a circuit and a current measuring unit for measuring the current through the functional circuit. The current measuring unit is connected to an output device in order to output the value of the measured current to an external test system via an external connection of the integrated circuit.
摘要翻译：本发明涉及具有用于测量通过功能电路的电流的电路和电流测量单元的集成电路。电流测量单元连接到输出设备，以通过集成电路的外部连接将测量电流的值输出到外部测试系统。

7. 发明授权

US06657452B2 Configuration for measurement of internal voltages of an integrated semiconductor apparatus 有权
标题翻译：用于测量集成半导体器件的内部电压的配置
公开(公告)号：US06657452B2
公开(公告)日：2003-12-02
申请号：US09740633
申请日：2000-12-18
申请人： Peter Beer , Carsten Ohlhoff
发明人： Peter Beer , Carsten Ohlhoff
IPC分类号： G01R3126
CPC分类号： G01R31/2884 , G01R19/165
摘要： The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).
摘要翻译：本发明涉及一种用于测量DUT（2）中的内部电压的配置，其中在每个DUT（2）中提供比较器（3），并将待测量的内部电压（Vint）与外部提供的基准电压（Vref）。

8. 发明申请

US20060242492A1 Method and apparatus for masking known fails during memory tests readouts 失效
公开(公告)号：US20060242492A1
公开(公告)日：2006-10-26
申请号：US11397790
申请日：2006-04-04
申请人： Jochen Hoffmann , Carsten Ohlhoff , Peter Beer
发明人： Jochen Hoffmann , Carsten Ohlhoff , Peter Beer
IPC分类号： G11C29/00
CPC分类号： G11C29/24
摘要： Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse. By masking the test results for memory elements (normal and redundant) that have been previously found defective, the memory elements may be tested in the same manner during front-end and back-end testing.

9. 发明授权

US07107501B2 Test device, test system and method for testing a memory circuit 有权
公开(公告)号：US07107501B2
公开(公告)日：2006-09-12
申请号：US10452485
申请日：2003-06-02
申请人： Carsten Ohlhoff , Peter Beer
发明人： Carsten Ohlhoff , Peter Beer
IPC分类号： G11C29/00 , G06F12/00
CPC分类号： G11C29/56012 , G11C29/56 , G11C2029/5606
摘要： A test device has an interface for connecting a memory circuit that is to be tested and for receiving fault addresses. The test device further has a fault address memory for storing fault addresses and a control unit for allocating the received fault addresses to a fault address which is to be stored. A first sequence of memory cells can be addressed with a first access time, and a second sequence of memory cells can be addressed with a second access time, in the fault address memory. The second access time is longer than the first access time. First fault addresses are received at a first data rate, and second fault addresses are received at a second data rate, via the interface. The second data rate is lower than the first data rate. The control unit stores the first fault addresses in the fault address memory on the basis of the first sequence of memory cells, and stores the second fault addresses in the fault address memory on a basis of the second sequence of memory cells.

10. 发明授权

US06671221B2 Semiconductor chip with trimmable oscillator 有权
公开(公告)号：US06671221B2
公开(公告)日：2003-12-30
申请号：US10154343
申请日：2002-05-23
申请人： Peter Beer , Carsten Ohlhoff
发明人： Peter Beer , Carsten Ohlhoff
IPC分类号： G11C818
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50012
摘要： A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the frequency of the oscillator and is implemented on the semiconductor chip. This guarantees a parallel setting of the oscillator frequency for a plurality of semiconductor chips without losses in yield or quality.

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