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1. 发明授权

EP0706267B1 An all-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages 失效
标题翻译：为总线，其由多个电源电压驱动的CMOS高阻抗输出缓冲
公开(公告)号：EP0706267B1
公开(公告)日：2000-11-08
申请号：EP95115235.4
申请日：1995-09-27
申请人： Pericom Semiconductor Corp.
发明人： Wong, Anthony Y. , Kwong, David , Yang, Lee , Hsiao, Charles
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H01L27/0218 , H01L27/11898 , H03K2217/0018

2. 发明公开

EP0706267A2 An all-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages 失效
标题翻译：用于由多个电源电压驱动的总线的全CMOS高阻输出缓冲器
公开(公告)号：EP0706267A2
公开(公告)日：1996-04-10
申请号：EP95115235.4
申请日：1995-09-27
申请人： Pericom Semiconductor Corp.
发明人： Wong, Anthony Y. , Kwong, David , Yang, Lee , Hsiao, Charles
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H01L27/0218 , H01L27/11898 , H03K2217/0018
摘要： An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.
摘要翻译：全CMOS输出缓冲器驱动可在3伏和5伏电压下工作的总线。处于高阻状态时，输出缓冲区吸收很少或不吸收电流。如果总线由外部设备驱动至5伏，则高阻抗输出缓冲器存在闩锁和总线逻辑电平失真的危险，因为它仅具有3伏电源并且不使用电荷泵或额外的5伏电源。偏置电路将包含p沟道晶体管和驱动器晶体管的N阱耦合到驱动到5伏的总线。因此，N井也被驱动到5伏，即公交车上的电压。高阻抗输出缓冲器中的p沟道驱动器晶体管的栅极也通过另一个p沟道晶体管耦合到N阱，将栅极电位升高到5伏。因此，p沟道驱动器晶体管的栅极和本体电压为5伏，消除了反向电流和闩锁问题。传输门将P沟道驱动晶体管的栅极与器件的其他电路隔离开来。传输门，偏置电路和驱动器晶体管的p沟道晶体管位于N阱中，仅在需要时偏置至5伏。因此，在正常操作期间，驱动器晶体管的N阱处于3伏特，消除了身体效应的性能损失。逻辑门增加了阱偏压，并且只在必要时隔离驱动器的门极，当总线为高电平并由5伏器件驱动时，输出缓冲器处于高阻状态。

3. 发明公开

EP0706267A3 An all-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages 失效
标题翻译：为总线，其由多个电源电压驱动的CMOS高阻抗输出缓冲
公开(公告)号：EP0706267A3
公开(公告)日：1996-09-25
申请号：EP95115235.4
申请日：1995-09-27
申请人： Pericom Semiconductor Corp.
发明人： Wong, Anthony Y. , Kwong, David , Yang, Lee , Hsiao, Charles
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H01L27/0218 , H01L27/11898 , H03K2217/0018
摘要： An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.

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