专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070186130A1 Reduced size transmission data packet header format for a medical device 审中-公开
标题翻译：减小医疗设备的传输数据包头数据格式
公开(公告)号：US20070186130A1
公开(公告)日：2007-08-09
申请号：US11522831
申请日：2006-09-18
申请人： Per Holm , Per Hansen , Morten Stribaek
发明人： Per Holm , Per Hansen , Morten Stribaek
IPC分类号： G06F11/00
CPC分类号： H04L1/0083 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0072
摘要： The present invention relates to a reduced size format for transmission packet header wherein a source address is encoded together with a check code in a medical device. The packet header thus contains one single field now in place of two i.e. the check code and source address. At the receiving end, the receiver looks up the sender address from the session descriptor table, calculates the check code and then performs the same encoding with the address and the check code, thus authenticating and validating the packet.
摘要翻译：本发明涉及用于传输分组报头的缩小尺寸格式，其中源地址与医疗设备中的校验码一起被编码。因此，分组报头包含现在代替两个单个字段，即检查码和源地址。在接收端，接收端从会话描述符表中查找发送方地址，计算校验码，然后用地址和校验码执行相同的编码，从而对数据包进行认证和验证。

2. 发明授权

US07860911B2 Extended precision accumulator 有权
标题翻译：扩展精密蓄能器
公开(公告)号：US07860911B2
公开(公告)日：2010-12-28
申请号：US11410146
申请日：2006-04-25
申请人： Morten Stribaek , Pascal Paillier
发明人： Morten Stribaek , Pascal Paillier
IPC分类号： G06F7/00
CPC分类号： G06F9/30032 , G06F7/5338 , G06F7/5443 , G06F7/724 , G06F7/725 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).
摘要翻译：乘法单元包括扩展精度累加器。提供微处理器指令，用于操纵扩展精度累加器的部分，包括将扩展累加器的一部分的内容移动到通用寄存器（“MFLHXU”）的指令以及移动通用寄存器的内容的指令到扩展累加器的一部分（“MTLHX”）。

3. 发明申请

US20070094482A1 Boundary address registers for selection of ISA mode 有权
标题翻译：用于选择ISA模式的边界地址寄存器
公开(公告)号：US20070094482A1
公开(公告)日：2007-04-26
申请号：US11636462
申请日：2006-12-11
申请人： Michael Jensen , Morten Stribaek
发明人： Michael Jensen , Morten Stribaek
IPC分类号： G06F9/40
CPC分类号： G06F9/44547 , G06F9/30076 , G06F9/30189 , G06F9/30196 , G06F9/3802
摘要： An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers. The ISA mode selection logic receives the particular address, and compares it against the plurality of address ranges to determine the particular ISA decoding mode for the particular program instruction.
摘要翻译：提供了一种装置和方法，其使多个指令集体系结构（ISA）中央处理单元（CPU）在执行多个ISA应用程序期间区分与不同ISA相对应的不同程序指令。该装置允许多ISA CPU选择与程序指令相对应的特定ISA解码模式。程序指令位于多ISA CPU的地址空间内的地址。该装置包括多个边界地址寄存器和ISA模式选择逻辑。可以动态地加载多个边界地址寄存器以将地址空间分割成多个地址范围，其中多个地址范围中的每一个对应于多个ISA解码模式中的每一个。 ISA模式选择逻辑耦合到多个边界地址寄存器。 ISA模式选择逻辑接收特定地址，并将其与多个地址范围进行比较，以确定特定程序指令的特定ISA解码模式。

4. 发明申请

US20060190519A1 Extended precision accumulator 有权
公开(公告)号：US20060190519A1
公开(公告)日：2006-08-24
申请号：US11410146
申请日：2006-04-25
申请人： Morten Stribaek , Pascal Paillier
发明人： Morten Stribaek , Pascal Paillier
IPC分类号： G06F7/52
CPC分类号： G06F9/30032 , G06F7/5338 , G06F7/5443 , G06F7/724 , G06F7/725 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).

5. 发明授权

US07509480B2 Selection of ISA decoding mode for plural instruction sets based upon instruction address 有权
标题翻译：基于指令地址选择多个指令集的ISA解码模式
公开(公告)号：US07509480B2
公开(公告)日：2009-03-24
申请号：US11636462
申请日：2006-12-11
申请人： Michael Gottlieb Jensen , Morten Stribaek
发明人： Michael Gottlieb Jensen , Morten Stribaek
IPC分类号： G06F9/30
CPC分类号： G06F9/44547 , G06F9/30076 , G06F9/30189 , G06F9/30196 , G06F9/3802
摘要： An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers. The ISA mode selection logic receives the particular address, and compares it against the plurality of address ranges to determine the particular ISA decoding mode for the particular program instruction.
摘要翻译：提供了一种装置和方法，其使多个指令集体系结构（ISA）中央处理单元（CPU）在执行多个ISA应用程序期间区分与不同ISA相对应的不同程序指令。该装置允许多ISA CPU选择与程序指令相对应的特定ISA解码模式。程序指令位于多ISA CPU的地址空间内的地址。该装置包括多个边界地址寄存器和ISA模式选择逻辑。可以动态地加载多个边界地址寄存器以将地址空间分割成多个地址范围，其中多个地址范围中的每一个对应于多个ISA解码模式中的每一个。 ISA模式选择逻辑耦合到多个边界地址寄存器。 ISA模式选择逻辑接收特定地址，并将其与多个地址范围进行比较，以确定特定程序指令的特定ISA解码模式。

6. 发明授权

US07318145B1 Random slip generator 有权
标题翻译：随机打滑发生器
公开(公告)号：US07318145B1
公开(公告)日：2008-01-08
申请号：US10141579
申请日：2002-05-09
申请人： Morten Stribaek , Jakob Schou Jensen , Jean-Francois Dhem
发明人： Morten Stribaek , Jakob Schou Jensen , Jean-Francois Dhem
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3836 , G06F9/3859 , G06F9/3861 , G06F21/556
摘要： A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be configurable so that the average frequency of random slips generated by the system may be set. Additional techniques are provided to make nullified instructions consume power like any other executing instruction.
摘要翻译：提供随机滑移发生器以减少侧向通道泄漏，从而阻止分析攻击，例如定时攻击和功率分析攻击。随机滑移生成可以是可配置的，使得可以设置由系统生成的随机滑移的平均频率。提供了额外的技术来使无效指令像任何其他执行指令一样消耗功率。

7. 发明授权

US07149878B1 Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values 有权
标题翻译：通过将当前指令执行地址与边界地址寄存器值进行比较来改变指令集架构模式
公开(公告)号：US07149878B1
公开(公告)日：2006-12-12
申请号：US09702112
申请日：2000-10-30
申请人： Michael Gottlieb Jensen , Morten Stribaek
发明人： Michael Gottlieb Jensen , Morten Stribaek
IPC分类号： G06F9/40
CPC分类号： G06F9/44547 , G06F9/30076 , G06F9/30189 , G06F9/30196 , G06F9/3802
摘要： An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers. The ISA mode selection logic receives the particular address, and compares it against the plurality of address ranges to determine the particular ISA decoding mode for the particular program instruction.
摘要翻译：提供了一种装置和方法，其使多个指令集体系结构（ISA）中央处理单元（CPU）在执行多个ISA应用程序期间区分与不同ISA相对应的不同程序指令。该装置允许多ISA CPU选择与程序指令相对应的特定ISA解码模式。程序指令位于多ISA CPU的地址空间内的地址。该装置包括多个边界地址寄存器和ISA模式选择逻辑。可以动态地加载多个边界地址寄存器以将地址空间分割成多个地址范围，其中多个地址范围中的每一个对应于多个ISA解码模式中的每一个。 ISA模式选择逻辑耦合到多个边界地址寄存器。 ISA模式选择逻辑接收特定地址，并将其与多个地址范围进行比较，以确定特定程序指令的特定ISA解码模式。

8. 发明授权

US07911952B1 Interface with credit-based flow control and sustained bus signals 有权
标题翻译：与信用流控制和持续总线信号接口
公开(公告)号：US07911952B1
公开(公告)日：2011-03-22
申请号：US10193682
申请日：2002-07-12
申请人： Flemming Nygreen , Morten Stribaek , Ole Kristian Friis , Kim Mostrup
发明人： Flemming Nygreen , Morten Stribaek , Ole Kristian Friis , Kim Mostrup
IPC分类号： H04J3/14 , H04J3/04
CPC分类号： H04L47/13 , H04L47/215
摘要： An interface between electronic devices uses a credit-based flow protocol with sustained bus signals. An initiating device waits for credit to issue a command to a target device. When credit is available, the initiating device issues the command to the target device such that the command is accessible by the target device until a new command is issued. The command may include a read or write request to the target device.
摘要翻译：电子设备之间的接口使用具有持续总线信号的基于信用的流量协议。发起设备等待授信向目标设备发出命令。当信用可用时，发起设备向目标设备发出命令，使得目标设备可以访问该命令，直到发出新的命令。该命令可以包括对目标设备的读取或写入请求。

9. 发明授权

US07181484B2 Extended-precision accumulation of multiplier output 有权
标题翻译：扩展精度积分乘法器输出
公开(公告)号：US07181484B2
公开(公告)日：2007-02-20
申请号：US09788685
申请日：2001-02-21
申请人： Morten Stribaek , Pascal Paillier
发明人： Morten Stribaek , Pascal Paillier
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F9/30032 , G06F7/5338 , G06F7/5443 , G06F7/724 , G06F7/725 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).
摘要翻译：乘法单元包括扩展精度累加器。提供微处理器指令，用于操纵扩展精度累加器的部分，包括将扩展累加器的一部分的内容移动到通用寄存器（“MFLHXU”）的指令以及移动通用寄存器的内容的指令到扩展累加器的一部分（“MTLHX”）。

10. 发明申请

US20060190518A1 Binary polynomial multiplier 有权
标题翻译：二进制多项式乘法器
公开(公告)号：US20060190518A1
公开(公告)日：2006-08-24
申请号：US09788670
申请日：2001-02-21
申请人： Hartvig Ekner , Morten Stribaek , Soeren Laursen
发明人： Hartvig Ekner , Morten Stribaek , Soeren Laursen
IPC分类号： G06F7/38
CPC分类号： G06F7/57 , G06F7/724
摘要： A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations.
摘要翻译：乘法单元包括对算术运算，二进制多项式运算和排列的支持。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式