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1. 发明申请

US20130178013A1 METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE 有权
标题翻译：制造门控二极管半导体器件的方法
公开(公告)号：US20130178013A1
公开(公告)日：2013-07-11
申请号：US13534983
申请日：2012-06-27
申请人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/34
CPC分类号： H01L29/22 , H01L29/66356 , H01L29/7391
摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates.
摘要翻译：本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体器件的方法。当栅极电压相对较高时，栅极下方的沟道具有n型，器件具有简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过栅极将n型ZnO转换成p型并使用NiO作为p型半导体，形成n-p-n-p掺杂结构。本发明特征在于能够通过高驱动电流和小的次阈值摆幅的优点来制造能够降低芯片功耗的栅极控制二极管器件的能力，特别适用于具有平板显示器的读写装置的制造，相变存储器以及基于柔性基板的半导体器件。

2. 发明授权

US08486754B1 Method for manufacturing a gate-control diode semiconductor device 有权
标题翻译：栅极控制二极管半导体器件的制造方法
公开(公告)号：US08486754B1
公开(公告)日：2013-07-16
申请号：US13534983
申请日：2012-06-27
申请人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/22 , H01L29/66356 , H01L29/7391
摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates.
摘要翻译：本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体器件的方法。当栅极电压相对较高时，栅极下方的沟道具有n型，器件具有简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过栅极将n型ZnO转换成p型并使用NiO作为p型半导体，形成n-p-n-p掺杂结构。本发明特征在于能够通过高驱动电流和小的次阈值摆幅的优点来制造能够降低芯片功耗的栅极控制二极管器件的能力，特别适用于具有平板显示器的读写装置的制造，相变存储器以及基于柔性基板的半导体器件。

3. 发明授权

US08426271B1 Method for manufacturing a gate-control diode semiconductor memory device 有权
标题翻译：栅极控制二极管半导体存储器件的制造方法
公开(公告)号：US08426271B1
公开(公告)日：2013-04-23
申请号：US13534998
申请日：2012-06-27
申请人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7781 , H01L29/66825 , H01L29/788
摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and the device is of a simple gate-control pn junction structure; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The quantity of charges in the floating gate determines the device threshold voltage, thus realizing the memory functions. This invention features capacity of manufacturing memory devices able to reduce the chip power consumption through advantages of high driving current and small sub threshold swing, is applicable to semiconductor memory devices manufacturing based on flexible substrates and flat panel displays and floating gate memories, etc.
摘要翻译：本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体存储器件的方法。当浮动栅极电压相对较高时，浮动栅极下的沟道为n型，器件具有简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过浮栅将n型ZnO反转为p型，并使用NiO作为p型半导体，形成n-p-n-p掺杂结构。浮栅中的电荷量决定了器件的阈值电压，从而实现了存储器的功能。本发明特征在于能够通过高驱动电流和小次阈值摆动的优点来制造能够降低芯片功耗的存储器件的能力，可应用于基于柔性基板和平板显示器以及浮动栅极存储器等的半导体存储器件制造。

4. 发明授权

US08685788B2 Nanowire tunneling field effect transistor with vertical structure and a manufacturing method thereof 失效
标题翻译：具有垂直结构的纳米线隧道场效应晶体管及其制造方法
公开(公告)号：US08685788B2
公开(公告)日：2014-04-01
申请号：US13528398
申请日：2012-06-20
申请人： Weining Bao , Chengwei Cao , Pengfei Wang , Wei Zhang
发明人： Weining Bao , Chengwei Cao , Pengfei Wang , Wei Zhang
IPC分类号： H01L21/16
CPC分类号： B82Y10/00 , B82Y40/00 , H01L29/0676 , H01L29/22 , H01L29/66356 , H01L29/7391
摘要： The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.
摘要翻译：本发明属于半导体器件的技术领域，具体涉及一种制造纳米线隧道场效应晶体管（TFET）的方法。在该方法中，所需的ZnO纳米线在水浴中开发而不需要高温高压，具有简单的溶液制备，开发方便，成本低廉，并且直接构成具有纳米线的垂直结构的MOS器件，因此在后续阶段省略纳米线治疗。本发明结构简单，制造方便，成本低，纳米线通道的开发控制和栅极的垂直结构的MOSFET阵列，有利于大规模MOSFET阵列的制造直。

5. 发明申请

US20130092902A1 NANOWIRE TUNNELING FIELD EFFECT TRANSISTOR WITH VERTICAL STRUCTURE AND A MANUFACTURING METHOD THEREOF 失效
标题翻译：具有垂直结构的纳米隧道场效应晶体管及其制造方法
公开(公告)号：US20130092902A1
公开(公告)日：2013-04-18
申请号：US13528398
申请日：2012-06-20
申请人： Weining Bao , Chengwei Cao , Pengfei Wang , Wei Zhang
发明人： Weining Bao , Chengwei Cao , Pengfei Wang , Wei Zhang
IPC分类号： H01L29/78 , H01L21/336 , B82Y40/00
CPC分类号： B82Y10/00 , B82Y40/00 , H01L29/0676 , H01L29/22 , H01L29/66356 , H01L29/7391
摘要： The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.
摘要翻译：本发明属于半导体器件的技术领域，具体涉及一种制造纳米线隧道场效应晶体管（TFET）的方法。在该方法中，所需的ZnO纳米线在水浴中开发而不需要高温高压，具有简单的溶液制备，开发方便，成本低廉，并且直接构成具有纳米线的垂直结构的MOS器件，因此在后续阶段省略纳米线治疗。本发明结构简单，制造方便，成本低，纳米线通道的开发控制和栅极的垂直结构的MOSFET阵列，有利于大规模MOSFET阵列的制造直。

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