专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07378341B2 Automatic process control of after-etch-inspection critical dimension 有权
标题翻译：蚀刻后检测临界尺寸的自动过程控制
公开(公告)号：US07378341B2
公开(公告)日：2008-05-27
申请号：US11382060
申请日：2006-05-08
申请人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76816 , H01L22/12
摘要： Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickness and the second thickness is substantially constant. An ADI CD of a contact hole to be formed on the substrate is altered and pre-determined based on the second thickness of the cap oxide layer. A photoresist layer is formed on the cap oxide layer. An opening having the predetermined ADI CD is formed in the photoresist layer. Using the photoresist layer as an etching mask, the cap oxide layer and the dielectric layer is etched through the opening to form a contact hole having an AEI CD.
摘要翻译：蚀刻后检测临界尺寸的自动过程控制。介电层沉积在衬底上，然后被平坦化为第一厚度。沉积具有第二厚度的帽氧化物层，其中第一厚度和第二厚度的组合基本上是恒定的。要形成在基板上的接触孔的ADI CD根据盖氧化物层的第二厚度改变并预先确定。在氧化膜层上形成光致抗蚀剂层。具有预定ADI CD的开口形成在光致抗蚀剂层中。使用光致抗蚀剂层作为蚀刻掩模，通过开口蚀刻帽氧化物层和电介质层，以形成具有AEI CD的接触孔。

2. 发明申请

US20070259527A1 AUTOMATIC PROCESS CONTROL OF AFTER-ETCH-INSPECTION CRITICAL DIMENSION 有权
标题翻译：后验检查关键尺寸的自动过程控制
公开(公告)号：US20070259527A1
公开(公告)日：2007-11-08
申请号：US11382060
申请日：2006-05-08
申请人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76816 , H01L22/12
摘要： Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickness and the second thickness is substantially constant. An ADI CD of a contact hole to be formed on the substrate is altered and pre-determined based on the second thickness of the cap oxide layer. A photoresist layer is formed on the cap oxide layer. An opening having the predetermined ADI CD is formed in the photoresist layer. Using the photoresist layer as an etching mask, the cap oxide layer and the dielectric layer is etched through the opening to form a contact hole having an AEI CD.
摘要翻译：蚀刻后检测临界尺寸的自动过程控制。介电层沉积在衬底上，然后被平坦化为第一厚度。沉积具有第二厚度的帽氧化物层，其中第一厚度和第二厚度的组合基本上是恒定的。要形成在基板上的接触孔的ADI CD根据盖氧化物层的第二厚度改变并预先确定。在氧化膜层上形成光致抗蚀剂层。具有预定ADI CD的开口形成在光致抗蚀剂层中。使用光致抗蚀剂层作为蚀刻掩模，通过开口蚀刻帽氧化物层和电介质层，以形成具有AEI CD的接触孔。

3. 发明授权

US07544623B2 Method for fabricating a contact hole 有权
标题翻译：接触孔的制造方法
公开(公告)号：US07544623B2
公开(公告)日：2009-06-09
申请号：US11530886
申请日：2006-09-11
申请人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76802 , H01L21/0271 , H01L21/0338 , H01L21/31138 , H01L21/31144
摘要： A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on the semiconductor substrate and the conductive region. An etching resistive layer is coated on the dielectric layer. A silicon-containing hard mask bottom anti-reflection coating (SHB) layer is then coated on the etching resistive layer. A photoresist layer is then coated on the SHB layer. A lithographic process is performed to form a first opening in the photoresist layer. Using the photoresist layer as a hard mask, the SHB layer is etched through the first opening, thereby forming a shrunk, tapered second opening in the SHB layer. Using the etching resistive layer as an etching hard mask, etching the dielectric layer through the second opening to form a contact hole in the dielectric layer.
摘要翻译：提供一种制造接触孔的方法。制备其上具有导电区域的半导体衬底。介电层沉积在半导体衬底和导电区域上。在电介质层上涂覆有蚀刻电阻层。然后将含硅硬掩模底部防反射涂层（SHB）层涂覆在蚀刻电阻层上。然后将光致抗蚀剂层涂覆在SHB层上。执行光刻工艺以在光致抗蚀剂层中形成第一开口。使用光致抗蚀剂层作为硬掩模，通过第一开口蚀刻SHB层，从而在SHB层中形成收缩的锥形第二开口。使用蚀刻电阻层作为蚀刻硬掩模，通过第二开口蚀刻电介质层，以在电介质层中形成接触孔。

4. 发明申请

US20080064203A1 METHOD FOR FABRICATING A CONTACT HOLE 有权
标题翻译：制作接触孔的方法
公开(公告)号：US20080064203A1
公开(公告)日：2008-03-13
申请号：US11530886
申请日：2006-09-11
申请人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
IPC分类号： H01L21/467
CPC分类号： H01L21/76802 , H01L21/0271 , H01L21/0338 , H01L21/31138 , H01L21/31144
摘要： A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on the semiconductor substrate and the conductive region. An etching resistive layer is coated on the dielectric layer. A silicon-containing hard mask bottom anti-reflection coating (SHB) layer is then coated on the etching resistive layer. A photoresist layer is then coated on the SHB layer. A lithographic process is performed to form a first opening in the photoresist layer. Using the photoresist layer as a hard mask, the SHB layer is etched through the first opening, thereby forming a shrunk, tapered second opening in the SHB layer. Using the etching resistive layer as an etching hard mask, etching the dielectric layer through the second opening to form a contact hole in the dielectric layer.
摘要翻译：提供一种制造接触孔的方法。制备其上具有导电区域的半导体衬底。介电层沉积在半导体衬底和导电区域上。在电介质层上涂覆有蚀刻电阻层。然后将含硅硬掩模底部防反射涂层（SHB）层涂覆在蚀刻电阻层上。然后将光致抗蚀剂层涂覆在SHB层上。执行光刻工艺以在光致抗蚀剂层中形成第一开口。使用光致抗蚀剂层作为硬掩模，通过第一开口蚀刻SHB层，从而在SHB层中形成收缩的锥形第二开口。使用蚀刻电阻层作为蚀刻硬掩模，通过第二开口蚀刻电介质层，以在电介质层中形成接触孔。

5. 发明申请

US20070202688A1 Method for forming contact opening 审中-公开
标题翻译：形成接触开口的方法
公开(公告)号：US20070202688A1
公开(公告)日：2007-08-30
申请号：US11361645
申请日：2006-02-24
申请人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Wen-Chou Tsai , Jiunn-Hsiung Liao
IPC分类号： H01L21/467
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802
摘要： A method for forming a contact opening is described. A substrate formed with a semiconductor device thereon is provided, and then an etch stop layer, a dielectric layer and a patterned photoresist layer are formed sequentially over the substrate. The exposed dielectric layer and 20% to 90% of the thickness of the exposed etch stop layer are removed to form an opening. After the patterned photoresist layer is removed, an etch step using a reaction gas is conducted to remove the etch stop layer remaining at the bottom of the opening and form a contact opening that exposes a part of the device, wherein the reaction gas is selected from CF4, CHF3 and CH2F2. By using the method, a micro-masking effect is avoided, and oxidation at the bottom of the contact opening conventionally caused by the photoresist removal using oxygen plasma is also avoided.
摘要翻译：描述形成接触开口的方法。提供了在其上形成有半导体器件的衬底，然后在衬底上顺序地形成蚀刻停止层，电介质层和图案化光致抗蚀剂层。暴露的介电层和暴露的蚀刻停止层的厚度的20％至90％被去除以形成开口。在去除图案化的光致抗蚀剂层之后，进行使用反应气体的蚀刻步骤以除去残留在开口底部的蚀刻停止层，并形成露出部分器件的接触开口，其中反应气体选自 CF 4，CH 3，CH 3和CH 2 2。通过使用该方法，避免了微掩蔽效应，并且也避免了常规由使用氧等离子体的光致抗蚀剂去除引起的接触开口底部的氧化。

6. 发明授权

US08236702B2 Method of fabricating openings and contact holes 有权
标题翻译：制造开口和接触孔的方法
公开(公告)号：US08236702B2
公开(公告)日：2012-08-07
申请号：US12042340
申请日：2008-03-05
申请人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
发明人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/76831 , H01L21/76897
摘要： A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.
摘要翻译：提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的半导体衬底。然后对电介质层和蚀刻停止层进行图案化以形成暴露半导体衬底的多个开口。随后形成介电薄膜以覆盖电介质层，开口的侧壁和半导体衬底。然后去除设置在电介质层和半导体衬底上的电介质薄膜，同时保留设置在侧壁上的电介质薄膜。

7. 发明申请

US20120184105A1 METHOD OF FORMING OPENINGS 有权
标题翻译：形成开口的方法
公开(公告)号：US20120184105A1
公开(公告)日：2012-07-19
申请号：US13431945
申请日：2012-03-27
申请人： Pei-Yu Chou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Jiunn-Hsiung Liao
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338
摘要： A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask.
摘要翻译：提供一种形成开口的方法。首先，提供其上具有含硅光刻胶层的基板。其次，在含硅光致抗蚀剂层上形成第一光刻胶图案。然后，通过使用第一光致抗蚀剂图案作为蚀刻掩模，在含硅光致抗蚀剂层上进行第一蚀刻步骤以形成多个第一开口。接下来，在含硅光致抗蚀剂层上形成第二光致抗蚀剂图案。然后，通过使用第二光致抗蚀剂图案作为蚀刻掩模，在含硅光致抗蚀剂层上进行第二蚀刻步骤以形成多个第二开口。

8. 发明申请

US20110223768A1 Method for Forming Contact Opening 审中-公开
标题翻译：形成接触开口的方法
公开(公告)号：US20110223768A1
公开(公告)日：2011-09-15
申请号：US12720671
申请日：2010-03-10
申请人： Ying-Chih LIN , Pei-Yu Chou , Jiunn-Hsiung Liao , Feng-Yi Chang , Chih-Wen Feng , Shang-Yuan Tsai
发明人： Ying-Chih LIN , Pei-Yu Chou , Jiunn-Hsiung Liao , Feng-Yi Chang , Chih-Wen Feng , Shang-Yuan Tsai
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/02063 , H01L21/76802 , H01L21/76814
摘要： A method for forming contact openings is provided. First, a semiconductor device is formed on a substrate. Next, an etching stop layer, a first dielectric layer and a patterned photoresist layer are sequentially formed on the substrate. Next a portion of the first dielectric layer and a portion of the etching stop layer are removed to form an opening, wherein the portion of the first dielectric layer and the portion of the etching stop layer are not covered by the patterned photoresist layer. Next, the patterned photoresist layer is removed. Next, an over etching process is performed to remove the etching stop layer at a bottom of the opening and expose the semiconductor device in a nitrogen-free environment. The reactant gas of the over etching process includes fluorine-containing hydrocarbons, hydrogen gas and argon gas.
摘要翻译：提供了形成接触开口的方法。首先，在基板上形成半导体装置。接下来，在衬底上依次形成蚀刻停止层，第一电介质层和图案化光致抗蚀剂层。接下来，去除第一电介质层的一部分和蚀刻停止层的一部分以形成开口，其中第一介电层的一部分和蚀刻停止层的部分不被图案化的光致抗蚀剂层覆盖。接下来，去除图案化的光致抗蚀剂层。接下来，进行过蚀刻处理以去除开口底部的蚀刻停止层，并在无氮环境中暴露半导体器件。过蚀刻工艺的反应气体包括含氟烃，氢气和氩气。

9. 发明申请

US20110076814A1 METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR 有权
标题翻译：制备应变硅CMOS晶体管的方法
公开(公告)号：US20110076814A1
公开(公告)日：2011-03-31
申请号：US12959393
申请日：2010-12-03
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
摘要翻译：首先，提供具有第一有源区和第二有源区的半导体基板。第一有源区包括第一晶体管，第二有源区包括第二晶体管。第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

10. 发明申请

US20110068408A1 STRAINED-SILICON CMOS TRANSISTOR 审中-公开
标题翻译：应变硅CMOS晶体管
公开(公告)号：US20110068408A1
公开(公告)日：2011-03-24
申请号：US12959399
申请日：2010-12-03
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained-silicon CMOS transistor includes: a semiconductor substrate having a first active region, a second active region, and an isolation structure disposed between the first active region and the second active region; a first transistor, disposed on the first active region; a second transistor, disposed on the second active region; a first etching stop layer, disposed on the first transistor and the second transistor; a first stress layer, disposed on the first transistor; a second etching stop layer, disposed on the first transistor and the first stress layer, wherein an edge of the first stress layer is aligned with that of the second etching stop layer; a second stress layer, disposed on the second transistor; and a third etching stop layer disposed on the second transistor and the second stress layer, wherein an edge of the second stress layer is aligned with that of the third etching stop layer.
摘要翻译：应变硅CMOS晶体管包括：具有第一有源区，第二有源区和设置在第一有源区和第二有源区之间的隔离结构的半导体衬底; 第一晶体管，设置在第一有源区上; 第二晶体管，设置在第二有源区上; 第一蚀刻停止层，设置在第一晶体管和第二晶体管上; 第一应力层，设置在所述第一晶体管上; 第二蚀刻停止层，设置在第一晶体管和第一应力层上，其中第一应力层的边缘与第二蚀刻停止层的边缘对准; 第二应力层，设置在所述第二晶体管上; 以及设置在所述第二晶体管和所述第二应力层上的第三蚀刻停止层，其中所述第二应力层的边缘与所述第三蚀刻停止层的边缘对准。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式