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1. 发明授权

US07268600B2 Phase- or frequency-locked loop circuit having a glitch detector for detecting triggering-edge-type glitches in a noisy signal 失效
标题翻译：相位或频率锁定环路电路具有用于检测噪声信号中的触发边缘型毛刺的毛刺检测器
公开(公告)号：US07268600B2
公开(公告)日：2007-09-11
申请号：US11164637
申请日：2005-11-30
申请人： Paul S. Carlile , Barton E. Green , Robert C. Jordan , Anthony J. Perri
发明人： Paul S. Carlile , Barton E. Green , Robert C. Jordan , Anthony J. Perri
IPC分类号： H03L7/00
CPC分类号： H03L7/199 , H03L7/0891
摘要： A phase- or frequency-locked loop circuit (200) that generates an accurate output signal (ACC_SYN_OUT) even in the presence of edge-triggering-type glitches (148, 304A, 304B) in the input reference clock signal (REF_CLK). The locked-loop circuit includes a phase or frequency difference detector (216) and a glitch detector (208) that generates a trigger signal (GLITCH_DETECTED) upon detection of at least one glitch. The trigger signal resets the difference detector so as to abort the updating of the output signal that the glitch would otherwise cause.
摘要翻译：即使在存在输入参考时钟信号（REF_CLK）中的边缘触发型毛刺（148,304A，304B））的情况下也产生精确输出信号（ACC_SYN_OUT）的相位锁相环或者锁相环电路（200）。锁定环电路包括相位或频率差检测器（216）和毛刺检测器（208），其在检测到至少一个毛刺时产生触发信号（GLITCH_DETECTED）。触发信号复位差分检测器，以便中止毛刺将导致的输出信号的更新。

2. 发明授权

US07915056B2 Image sensor monitor structure in scribe area 失效
标题翻译：图像传感器监控结构在划片区域
公开(公告)号：US07915056B2
公开(公告)日：2011-03-29
申请号：US12051868
申请日：2008-03-20
申请人： John J. Ellis-Monaghan , Mark D. Jaffe , Sambasivan Narayan , Anthony J. Perri , Richard J. Rassel , Tian Xia
发明人： John J. Ellis-Monaghan , Mark D. Jaffe , Sambasivan Narayan , Anthony J. Perri , Richard J. Rassel , Tian Xia
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.
摘要翻译：设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

3. 发明申请

US20080164403A1 Wide Dynamic Range Sensor 审中-公开
标题翻译：宽动态范围传感器
公开(公告)号：US20080164403A1
公开(公告)日：2008-07-10
申请号：US11620062
申请日：2007-01-05
申请人： Ezra D. Hall , Anthony J. Perri
发明人： Ezra D. Hall , Anthony J. Perri
IPC分类号： H01L27/146
CPC分类号： H04N5/37452 , H04N5/3559 , H04N5/37455
摘要： A sensor and method for widening a dynamic range of sensor circuitry for sensing energy, such as light energy. The sensor circuitry includes a sensor and recharge circuitry for sharing additional charge with the sensor as needed during an integration period. Readout circuitry is provided to read out, after the integration period, the sense voltage remaining across the sensor and recharge information indicating whether the recharge circuitry shared charge with the sensor during the integration period. The sense voltage and recharge information read out of the sensor circuitry is used in a function to determine the total amount of energy sensed by the sensor during the integration period.
摘要翻译：用于加宽用于感测能量的传感器电路的动态范围的传感器和方法，例如光能。传感器电路包括传感器和再充电电路，用于在集成期间根据需要与传感器共享额外的电荷。提供读出电路，用于在积分期间之后读出传感器周围剩余的检测电压，并在充电期间再次充电指示再生电路是否与传感器共用电荷。在传感器电路读出的感测电压和再充电信息用于确定在积分期间由传感器感测到的总能量的功能。

4. 发明授权

US5396636A Remote power control via data link 失效
标题翻译：通过数据链路进行远程电源控制
公开(公告)号：US5396636A
公开(公告)日：1995-03-07
申请号：US779690
申请日：1991-10-21
申请人： Robert J. Gallagher , Karl H. Hoppe , Anthony J. Perri , Mark S. Styduhar , Jordan M. Taylor , Bert W. Weidle
发明人： Robert J. Gallagher , Karl H. Hoppe , Anthony J. Perri , Mark S. Styduhar , Jordan M. Taylor , Bert W. Weidle
IPC分类号： G06F1/26 , G06F1/32 , G06F13/00 , G06F11/00
CPC分类号： G06F1/3209
摘要： An inexpensive and low power consumption power control unit that does not require a separate interface or network. In the power off state only a detector and a power controller require power, this power is supplied from a power source. Upon detection of traffic a frame decoder is powered up to receive frames. When the link is quiet, the decoder is powered down while the power controller and receiver remain powered and await further traffic.
摘要翻译：廉价且功耗低的功率控制单元，不需要单独的接口或网络。在断电状态下，只有一个检测器和一个电源控制器需要电源，此电源由电源提供。在检测到业务时，帧解码器被加电以接收帧。当链路静音时，解码器掉电，同时电源控制器和接收器保持供电并等待进一步的流量。

5. 发明申请

US20080186069A1 DESIGN STRUCTURE FOR DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL 有权
标题翻译：动态锁定状态节省设备和协议的设计结构
公开(公告)号：US20080186069A1
公开(公告)日：2008-08-07
申请号：US12099423
申请日：2008-04-08
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
IPC分类号： H03K3/00
CPC分类号： G11C5/145 , H03K3/356008
摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译：本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。

6. 发明申请

US20080062748A1 DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL 失效
标题翻译：动态锁定状态保存设备和协议
公开(公告)号：US20080062748A1
公开(公告)日：2008-03-13
申请号：US11530981
申请日：2006-09-12
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
IPC分类号： G11C11/00
CPC分类号： G11C5/141 , G11C5/143 , G11C14/00
摘要： The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译：本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。

7. 发明授权

US06650190B2 Ring oscillator with adjustable delay 失效
公开(公告)号：US06650190B2
公开(公告)日：2003-11-18
申请号：US09832712
申请日：2001-04-11
申请人： Richard Jordan , Anthony J. Perri
发明人： Richard Jordan , Anthony J. Perri
IPC分类号： H03K3354
CPC分类号： H03K3/0315 , H03K5/133 , H03K2005/00065
摘要： A variable-frequency digital ring oscillator provides small and consistent frequency adjustments throughout a locked range. The ring oscillator of the invention is standard cell placeable and operates at the technology limits to provide small and precise delay changes that is inexpensive to implement. The digital variable-frequency ring oscillator includes multiple macro delay elements forming an inverter ring circuit, each element having an individual macro delay unit that in turn is comprised of multiple adjustable delay units. All of these adjustable delay units are controlled by a single delay control signal.

8. 发明授权

US08239811B2 System and method for wireless and dynamic intra-process measurement of integrated circuit parameters 有权
标题翻译：集成电路参数的无线和动态过程内测量的系统和方法
公开(公告)号：US08239811B2
公开(公告)日：2012-08-07
申请号：US12053705
申请日：2008-03-24
申请人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D. B. Hall , Anthony J. Perri , Sebastian T. Ventrone
发明人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D. B. Hall , Anthony J. Perri , Sebastian T. Ventrone
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： H04Q9/00 , H01L22/12 , H01L22/14 , H01L22/26 , H01L23/64 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.
摘要翻译：公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。无源电路可以在和/或处理步骤之间进行无线询问。然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。

9. 发明授权

US07966589B2 Structure for dynamic latch state saving device and protocol 有权
标题翻译：动态锁存状态保存装置和协议的结构
公开(公告)号：US07966589B2
公开(公告)日：2011-06-21
申请号：US12099423
申请日：2008-04-08
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
IPC分类号： G06F17/50
CPC分类号： G11C5/145 , H03K3/356008
摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译：本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。

10. 发明申请

US20090237103A1 IMAGE SENSOR MONITOR STRUCTURE IN SCRIBE AREA 失效
标题翻译：图像传感器监控结构在SCRIBE区域
公开(公告)号：US20090237103A1
公开(公告)日：2009-09-24
申请号：US12051868
申请日：2008-03-20
申请人： John J. Ellis-Monaghan , Mark D. Jaffe , Sambasivan Narayan , Anthony J. Perri , Richard J. Rassel , Tian Xia
发明人： John J. Ellis-Monaghan , Mark D. Jaffe , Sambasivan Narayan , Anthony J. Perri , Richard J. Rassel , Tian Xia
IPC分类号： G01R31/26 , H01L23/00 , G06F17/50
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.
摘要翻译：设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

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