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1. 发明授权

US07126212B2 Three dimensional device integration method and integrated device 有权
公开(公告)号：US07126212B2
公开(公告)日：2006-10-24
申请号：US10011432
申请日：2001-12-11
申请人： Paul M. Enquist , Gaius Fountain
发明人： Paul M. Enquist , Gaius Fountain
IPC分类号： H01L29/08
CPC分类号： H01L24/08 , H01L21/187 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/26 , H01L24/27 , H01L24/30 , H01L24/48 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2223/6677 , H01L2224/0807 , H01L2224/08123 , H01L2224/1134 , H01L2224/16 , H01L2224/24011 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/3005 , H01L2224/30104 , H01L2224/305 , H01L2224/48091 , H01L2224/48101 , H01L2224/48227 , H01L2224/48247 , H01L2224/80896 , H01L2224/81894 , H01L2224/8303 , H01L2224/83092 , H01L2224/83099 , H01L2224/8319 , H01L2224/83193 , H01L2224/83345 , H01L2224/83359 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83912 , H01L2224/83948 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , Y10S148/012 , Y10S438/977 , H01L2224/13099 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

2. 发明申请

US20080063878A1 Method for low temperature bonding and bonded structure 有权
公开(公告)号：US20080063878A1
公开(公告)日：2008-03-13
申请号：US11980415
申请日：2007-10-31
申请人： Qin-Yi Tong , Gaius Fountain , Paul Enquist
发明人： Qin-Yi Tong , Gaius Fountain , Paul Enquist
IPC分类号： H01L21/20 , B32B9/04
CPC分类号： H01L24/83 , H01L21/0206 , H01L21/2007 , H01L21/31105 , H01L21/31116 , H01L21/322 , H01L21/76251 , H01L24/26 , H01L24/75 , H01L25/0657 , H01L25/50 , H01L27/085 , H01L29/06 , H01L29/16 , H01L2224/8301 , H01L2224/8303 , H01L2224/83031 , H01L2224/8309 , H01L2224/83099 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83948 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/0106 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01084 , H01L2924/01093 , H01L2924/0132 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , Y10S148/012 , Y10S438/974 , Y10T156/10 , Y10T156/1043 , H01L2924/01014 , H01L2924/01015 , H01L2924/01049 , H01L2924/01031 , H01L2924/3512 , H01L2924/00
摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

3. 发明申请

US20080053959A1 Method for low temperature bonding and bonded structure 有权
标题翻译：低温接合方法和接合结构
公开(公告)号：US20080053959A1
公开(公告)日：2008-03-06
申请号：US11980664
申请日：2007-10-31
申请人： Qin-Yi Tong , Gaius Fountain , Paul Enquist
发明人： Qin-Yi Tong , Gaius Fountain , Paul Enquist
IPC分类号： C23F1/00 , C03B29/00
CPC分类号： H01L24/83 , H01L21/0206 , H01L21/2007 , H01L21/31105 , H01L21/31116 , H01L21/322 , H01L21/76251 , H01L24/26 , H01L24/75 , H01L25/0657 , H01L25/50 , H01L27/085 , H01L29/06 , H01L29/16 , H01L2224/8301 , H01L2224/8303 , H01L2224/83031 , H01L2224/8309 , H01L2224/83099 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83948 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/0106 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01084 , H01L2924/01093 , H01L2924/0132 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , Y10S148/012 , Y10S438/974 , Y10T156/10 , Y10T156/1043 , H01L2924/01014 , H01L2924/01015 , H01L2924/01049 , H01L2924/01031 , H01L2924/3512 , H01L2924/00
摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
摘要翻译：在低温或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。一种蚀刻方法该方法还可以包括除去界面聚合的副产物，以防止反向聚合反应以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中冲洗以促进在表面上形成所需的粘结物质。

4. 发明申请

US20060292744A1 Three dimensional device integration method and integrated device 审中-公开
公开(公告)号：US20060292744A1
公开(公告)日：2006-12-28
申请号：US11514083
申请日：2006-09-01
申请人： Paul Enquist , Gaius Fountain
发明人： Paul Enquist , Gaius Fountain
IPC分类号： H01L21/00
CPC分类号： H01L24/08 , H01L21/187 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/26 , H01L24/27 , H01L24/30 , H01L24/48 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2223/6677 , H01L2224/0807 , H01L2224/08123 , H01L2224/1134 , H01L2224/16 , H01L2224/24011 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/3005 , H01L2224/30104 , H01L2224/305 , H01L2224/48091 , H01L2224/48101 , H01L2224/48227 , H01L2224/48247 , H01L2224/80896 , H01L2224/81894 , H01L2224/8303 , H01L2224/83092 , H01L2224/83099 , H01L2224/8319 , H01L2224/83193 , H01L2224/83345 , H01L2224/83359 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83912 , H01L2224/83948 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , Y10S148/012 , Y10S438/977 , H01L2224/13099 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

5. 发明申请

US20050009246A1 Wafer bonding hermetic encapsulation 有权
标题翻译：晶圆粘合气密封装
公开(公告)号：US20050009246A1
公开(公告)日：2005-01-13
申请号：US10913357
申请日：2004-08-09
申请人： Paul Enquist , Qin-Yi Tong , Gaius Fountain , Robert Markunas
发明人： Paul Enquist , Qin-Yi Tong , Gaius Fountain , Robert Markunas
IPC分类号： B81B7/00 , H01L21/50 , H01L23/10 , H01L21/44
CPC分类号： B81C1/00269 , B81C2203/0118 , H01L21/50 , H01L23/10 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： A method for providing encapsulation of an electronic device which obtains an encapsulating member configured to enclose the electronic device, prepares a surface of the encapsulating member for non-adhesive direct bonding, prepares a surface of a device carrier including the electronic device for non-adhesive direct bonding, and bonds the prepared surface of the encapsulating member to the prepared surface of the device carrier to form an encapsulation of the electronic device. As such, an encapsulated electronic device results which includes the device carrier having a first bonding region encompassing the electronic device, includes the encapsulating member having at least one relief preventing contact between the electronic device and the encapsulating member and having a second bonding region bonded to the first bonding region of the device carrier, and includes a non-adhesive direct bond formed between the first and second bonding regions thereby to form an encapsulation of the electronic device. The encapsulated electronic device can be an electronic or optoelectronic device.
摘要翻译：一种用于提供电子设备的封装的方法，该电子设备获得构造成封闭电子设备的封装构件，准备用于非粘合剂直接接合的封装构件的表面，准备包括用于非粘合剂的电子设备的设备载体的表面直接结合，并将封装构件的制备表面粘合到装置载体的制备表面上以形成电子器件的封装。因此，包括具有包围电子设备的第一接合区域的器件载体的封装的电子器件包括具有至少一个防止接触电子器件与封装元件之间的防止接触的封装元件，并且具有第二接合区域装置载体的第一结合区域，并且包括在第一和第二接合区域之间形成的非粘合性直接结合，从而形成电子器件的封装。封装的电子器件可以是电子或光电器件。

6. 发明申请

US20080093747A1 Three dimensional device integration method and integrated device 审中-公开
公开(公告)号：US20080093747A1
公开(公告)日：2008-04-24
申请号：US11980665
申请日：2007-10-31
申请人： Paul Enquist , Gaius Fountain
发明人： Paul Enquist , Gaius Fountain
IPC分类号： H01L23/52 , H01L21/98
CPC分类号： H01L24/08 , H01L21/187 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/26 , H01L24/27 , H01L24/30 , H01L24/48 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2223/6677 , H01L2224/0807 , H01L2224/08123 , H01L2224/1134 , H01L2224/16 , H01L2224/24011 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/3005 , H01L2224/30104 , H01L2224/305 , H01L2224/48091 , H01L2224/48101 , H01L2224/48227 , H01L2224/48247 , H01L2224/80896 , H01L2224/81894 , H01L2224/8303 , H01L2224/83092 , H01L2224/83099 , H01L2224/8319 , H01L2224/83193 , H01L2224/83345 , H01L2224/83359 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83912 , H01L2224/83948 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , Y10S148/012 , Y10S438/977 , H01L2224/13099 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

7. 发明申请

US20080061419A1 Three dimensional device integration method and integrated device 审中-公开
标题翻译：三维设备集成方法和集成设备
公开(公告)号：US20080061419A1
公开(公告)日：2008-03-13
申请号：US11980659
申请日：2007-10-31
申请人： Paul Enquist , Gaius Fountain
发明人： Paul Enquist , Gaius Fountain
IPC分类号： H01L29/08 , H01L29/06
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5389 , H01L24/26 , H01L24/80 , H01L24/82 , H01L24/83 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2221/6835 , H01L2221/68363 , H01L2224/24 , H01L2224/24011 , H01L2224/24051 , H01L2224/24145 , H01L2224/24146 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/80896 , H01L2224/81894 , H01L2224/8385 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/82 , H01L2924/00012 , H01L2224/8203 , H01L2224/821 , H01L2224/80001
摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.
摘要翻译：一种器件集成方法和集成器件。该方法可以包括将具有衬底的半导体器件直接接合到元件的步骤; 以及去除所述衬底的一部分以在结合之后露出所述半导体器件的剩余部分。元件可以包括用于热扩散，阻抗匹配或RF隔离的衬底之一，天线以及由无源元件组成的匹配网络。第二热扩散基板可以结合到半导体器件的其余部分。互连可以通过第一或第二基底进行。该方法还可以包括将多个半导体器件接合到元件，并且元件可以具有设置半导体器件的凹部。具有多个接触结构的导体阵列可以形成在半导体器件的暴露表面上，可以通过半导体器件到器件区域形成通孔，并且可以在所述器件区域和所述接触结构之间形成互连。

8. 发明申请

US20050079712A1 Method for low temperature bonding and bonded structure 有权
标题翻译：低温接合方法和接合结构
公开(公告)号：US20050079712A1
公开(公告)日：2005-04-14
申请号：US10913441
申请日：2004-08-09
申请人： Qin-Yi Tong , Gaius Fountain , Paul Enquist
发明人： Qin-Yi Tong , Gaius Fountain , Paul Enquist
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/20 , H01L21/58 , H01L21/30 , H01L21/302 , H01L21/46 , H01L21/461
CPC分类号： H01L24/83 , H01L21/0206 , H01L21/2007 , H01L21/31105 , H01L21/31116 , H01L21/322 , H01L21/76251 , H01L24/26 , H01L24/75 , H01L25/0657 , H01L25/50 , H01L27/085 , H01L29/06 , H01L29/16 , H01L2224/8301 , H01L2224/8303 , H01L2224/83031 , H01L2224/8309 , H01L2224/83099 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83948 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/0106 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01084 , H01L2924/01093 , H01L2924/0132 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , Y10S148/012 , Y10S438/974 , Y10T156/10 , Y10T156/1043 , H01L2924/01014 , H01L2924/01015 , H01L2924/01049 , H01L2924/01031 , H01L2924/3512 , H01L2924/00
摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
摘要翻译：在低温或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。一种蚀刻方法该方法还可以包括除去界面聚合的副产物以防止反向聚合反应，以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中冲洗以促进在表面上形成所需的粘结物质。

9. 发明申请

US20080061418A1 Three dimensional device integration method and integrated device 审中-公开
公开(公告)号：US20080061418A1
公开(公告)日：2008-03-13
申请号：US11980452
申请日：2007-10-31
申请人： Paul Enquist , Gaius Fountain
发明人： Paul Enquist , Gaius Fountain
IPC分类号： H01L29/08 , H01L29/06
CPC分类号： H01L24/08 , H01L21/187 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/26 , H01L24/27 , H01L24/30 , H01L24/48 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2223/6677 , H01L2224/0807 , H01L2224/08123 , H01L2224/1134 , H01L2224/16 , H01L2224/24011 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/3005 , H01L2224/30104 , H01L2224/305 , H01L2224/48091 , H01L2224/48101 , H01L2224/48227 , H01L2224/48247 , H01L2224/80896 , H01L2224/81894 , H01L2224/8303 , H01L2224/83092 , H01L2224/83099 , H01L2224/8319 , H01L2224/83193 , H01L2224/83345 , H01L2224/83359 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83912 , H01L2224/83948 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , Y10S148/012 , Y10S438/977 , H01L2224/13099 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

10. 发明申请

US20070037379A1 3D IC method and device 有权
标题翻译： 3D IC方法和装置
公开(公告)号：US20070037379A1
公开(公告)日：2007-02-15
申请号：US11201321
申请日：2005-08-11
申请人： Paul Enquist , Gaius Fountain , Qin-Yi Tong
发明人： Paul Enquist , Gaius Fountain , Qin-Yi Tong
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/81121 , H01L2224/81201 , H01L2224/8123 , H01L2224/81801 , H01L2224/81894 , H01L2224/81931 , H01L2224/83894 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2224/81
摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.
摘要翻译：三维集成元件如单片或晶片的方法以及具有诸如单模裸片或晶片的连接元件的集成结构。芯片和晶片中的任一个或两者可以具有形成在其中的半导体器件。具有第一接触结构的第一元件被结合到具有第二接触结构的第二元件。第一和第二接触结构可以在结合时暴露，并且由于接合而电连接。可以在接合之后蚀刻和填充通孔，以暴露并形成互连的第一和第二接触结构的电互连并提供从表面到该互连的电接入。或者，第一接触结构和/或第二接触结构在接合时不暴露，并且在接合之后蚀刻并填充通孔以将第一和第二接触结构电互连并且提供对互连的第一和第二接触结构到表面的电接触。此外，器件可以形成在第一衬底中，该器件设置在第一衬底的器件区域中并且具有第一接触结构。通孔可以在结合之前被蚀刻或蚀刻和填充穿过器件区域并进入第一衬底，并且第一衬底被稀释以暴露通孔，或者在结合之后填充通孔。

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