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1. 发明授权

US06223230B1 Direct memory access in a bridge for a multi-processor system 失效
标题翻译：用于多处理器系统的桥接器中的直接存储器访问
公开(公告)号：US06223230B1
公开(公告)日：2001-04-24
申请号：US09094842
申请日：1998-06-15
申请人： Paul Jeffrey Garnett , Stephen Rowlinson , Femi A. Oyelakin
发明人： Paul Jeffrey Garnett , Stephen Rowlinson , Femi A. Oyelakin
IPC分类号： G06F1300
CPC分类号： G06F11/2289 , G06F13/404
摘要： A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set, and a device bus. A bridge control mechanism is configured to provide geographic addressing for devices on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range. A different geographic address range can allocated to each of a plurality of device slots on the device bus. A different geographic address range can also be allocated to the processor set resources (e.g., processor set memory). An address decoding mechanism maintain geographic address mappings, and verifies geographic addresses for direct memory access. The geographic address mappings can be configured in random access memory of the bridge. A slot response register is associated with each slot on the device bus. The slot response register records ownership of a device by the processing sets. The bridge control mechanism responds to a direct memory access request from a device on the device bus to access the slot response register for the slot for the requesting device for identifying the owning processor set, for enabling access to the memory of the owning processor set. The slot response registers can be configured in random access memory in the bridge.
摘要翻译：用于多处理器系统的桥包括用于连接到第一处理集合的I / O总线，第二处理集合的I / O总线和设备总线的总线接口。桥接控制机构被配置为为设备总线上的设备提供地理寻址，并且响应来自设备总线上的设备的请求，以直接访问处理集合的资源，以验证设备提供的地址是否下降在正确的地理范围内。不同的地理位置范围可以分配给设备总线上的多个设备时隙中的每一个。也可以将不同的地理区域范围分配给处理器集资源（例如，处理器集存储器）。地址解码机制保持地理地址映射，并验证地理地址以进行直接存储器访问。可以在桥接器的随机存取存储器中配置地理地址映射。插槽响应寄存器与设备总线上的每个插槽相关联。槽响应寄存器通过处理集来记录设备的所有权。桥接控制机制响应来自设备总线上的设备的直接存储器访问请求，以访问用于请求设备的时隙的时隙响应寄存器，用于识别拥有处理器集，以使得能够访问所拥有的处理器集的存储器。插槽响应寄存器可以在桥中的随机存取存储器中进行配置。

2. 发明授权

US5903233A Extended binary apparatus and method 失效
标题翻译：扩展二进制装置和方法
公开(公告)号：US5903233A
公开(公告)日：1999-05-11
申请号：US882194
申请日：1997-06-25
申请人： Paul Jeffrey Garnett
发明人： Paul Jeffrey Garnett
IPC分类号： H03M5/06 , H03M5/16 , H03M7/12
CPC分类号： H03M5/06 , H03M5/16
摘要： An extended binary encoding for a plurality of inputs is sensed using a two-phase process. In a first phase binary values are sensed at the inputs. In the second phase, inputs sensed as having a first binary signal value are driven to a second binary value to test whether other inputs which had the first binary signal value also change to the second binary value indicative of a direct connection between the inputs. Accordingly, an enhanced binary encoding is achieved by evaluating not only the binary signal value at the inputs, but also which inputs are connected together, the selective interconnection of inputs extending the 2.sup.N options available for conventional binary encoding.
摘要翻译：使用两相处理来感测用于多个输入的扩展二进制编码。在第一阶段，输入端检测到二进制值。在第二阶段中，感测为具有第一二进制信号值的输入被驱动到第二二进制值，以测试具有第一二进制信号值的其它输入是否也改变为指示输入之间的直接连接的第二二进制值。因此，增强的二进制编码通过不仅评估输入端的二进制信号值，而且通过评估连接在一起的输入，扩展可用于常规二进制编码的2N个选项的输入的选择性互连来实现。

3. 发明授权

US07690888B2 Fan grill 有权
标题翻译：风扇格栅
公开(公告)号：US07690888B2
公开(公告)日：2010-04-06
申请号：US10809138
申请日：2004-03-25
申请人： Paul Jeffrey Garnett
发明人： Paul Jeffrey Garnett
IPC分类号： F04D29/70
CPC分类号： F04D29/703
摘要： The present invention provides a grill 10 for use in electrical equipment comprising a fan. The grill 10 comprises a substantially planar portion 90 that provides protection for (and indeed from) the blades of a fan and a handle 100 that provides means by which the grill may be held. The substantially planar portion 90 may comprise an opening 94 that facilitates stacking of a plurality of like grills 10.
摘要翻译：本发明提供一种用于包括风扇的电气设备的格栅10。格栅10包括大致平坦的部分90，其为风扇的叶片提供保护（并且实际上来自）以及提供可以保持格栅的装置的手柄100。基本平坦的部分90可以包括便于堆叠多个类似格栅10的开口94。

4. 发明授权

US07227748B2 Cooling module 有权
标题翻译：冷却模块
公开(公告)号：US07227748B2
公开(公告)日：2007-06-05
申请号：US10403670
申请日：2003-03-31
申请人： Paul Jeffrey Garnett
发明人： Paul Jeffrey Garnett
IPC分类号： H05K7/20
CPC分类号： G06F1/20 , H05K7/20172
摘要： A cooling module is provided for an electrically powered apparatus. The cooling module comprises a non-volatile memory arranged to store a module identifier code for the module.
摘要翻译：为电动设备提供冷却模块。冷却模块包括布置成存储模块的模块标识符代码的非易失性存储器。

5. 发明授权

US06785777B2 Control logic for memory modification tracking with hierarchical dirty indicators 有权
标题翻译：带有分级脏指示器的存储器修改跟踪控制逻辑
公开(公告)号：US06785777B2
公开(公告)日：2004-08-31
申请号：US09939078
申请日：2001-08-24
申请人： Paul Jeffrey Garnett , Jeremy Graham Harris
发明人： Paul Jeffrey Garnett , Jeremy Graham Harris
IPC分类号： G06F1212
CPC分类号： G06F11/1658 , G06F12/08 , G06F12/10 , G06F13/4027
摘要： A dirty memory that includes dirty indicators settable to indicate dirtied pages of memory is provided with control logic operable automatically to interrogate the dirty memory to identify dirty indicators that are set. Implementing the control of the dirty RAM in hardware or firmware enables interrogation of the dirty RAM to identify set dirty indicators in a rapid and reliable manner. The control logic can advantageously be operable to interrogate the dirty memory word-by-word to determine words including a set bit. A comparator can be provided for comparing bits of a word to a predetermined value to determine where a dirty indicator is set. The comparison could be performed serially for bits within a word, but it is advantageously done in parallel for the bits of the word. For example, by using associative memory, the interrogation of the dirty memory could be effected associatively in parallel to determine words including a word with a set bit. Address logic enables a determination of a memory page address corresponding to a set dirty indicator. This can be effected by computing the page address given a known dirty bit location and a known mapping between the dirty memory and main memory.
摘要翻译：包含可设置为指示脏的页面的脏指示器的脏内存提供有控制逻辑，其可自动操作以询问脏存储器以识别设置的脏指示器。在硬件或固件中实现对脏RAM的控制，可以询问脏RAM以快速可靠的方式识别设置的脏指示器。控制逻辑可以有利地用于逐个询问脏存储器以确定包括设定位的字。可以提供比较器，用于将字的位与预定值进行比较，以确定脏指示器的设置位置。该比较可以串行地执行一个单词内的比特，但是对于单词的比特来说，有利地并行地进行比较。例如，通过使用关联存储器，可以并行地相关地实现脏存储器的询问，以确定包括具有设置位的字的单词。地址逻辑使得能够确定与设定的脏指示符相对应的存储器页地址。这可以通过计算给定已知脏位位置的页面地址和脏存储器和主存储器之间的已知映射来实现。

6. 发明授权

US07129851B1 Indicator feedback mechanism 有权
标题翻译：指标反馈机制
公开(公告)号：US07129851B1
公开(公告)日：2006-10-31
申请号：US10673696
申请日：2003-09-29
申请人： Paul Jeffrey Garnett
发明人： Paul Jeffrey Garnett
IPC分类号： G09F9/33
CPC分类号： G06F1/18 , H05K5/0017
摘要： An indicator assembly for a computer system can comprise a light guide for directing light from an indicator light source to an exterior panel of the computer system. The assembly can also comprise a photodetector configured to receive a portion of the light transmitted by the light guide. The photodetector can produce a signal representative of the portion of light received. For example, the photodetector may produce a signal representative of the color and/or intensity of the portion of light received. Using the signal representative of the portion of light received, components such as a controller can test for the presence of faults.
摘要翻译：用于计算机系统的指示器组件可以包括用于将来自指示器光源的光引导到计算机系统的外部面板的光导。组件还可以包括被配置为接收由光导传输的光的一部分的光电检测器。光电检测器可以产生表示所接收的光的部分的信号。例如，光电检测器可以产生表示所接收的光的部分的颜色和/或强度的信号。使用表示所接收的光的部分的信号，诸如控制器的组件可以测试故障的存在。

7. 发明授权

US06999312B1 Heatsink apparatus 有权
标题翻译：散热器
公开(公告)号：US06999312B1
公开(公告)日：2006-02-14
申请号：US10403668
申请日：2003-03-31
申请人： Paul Jeffrey Garnett , Jay Kevin Osborn , Andrew Stephen Burnham
发明人： Paul Jeffrey Garnett , Jay Kevin Osborn , Andrew Stephen Burnham
IPC分类号： G06F1/20
CPC分类号： H01L23/467 , H01L2924/0002 , H01L2924/00
摘要： There is provided a computing apparatus. The computing apparatus has first and second computing elements and a heatsink thermally coupled to each of the first and second computing elements. A portion of the heatsink thermally coupled to the first computing element is thermally separated from a portion of the heatsink thermally coupled to the second computing element by a region having a reduced thermal conductivity.
摘要翻译：提供了一种计算装置。计算设备具有第一和第二计算元件以及热耦合到第一和第二计算元件中的每一个的散热器。热耦合到第一计算元件的散热器的一部分通过热导率降低的区域与散热器的热耦合到第二计算元件的部分热分离。

8. 发明授权

US06981172B2 Protection for memory modification tracking 有权
标题翻译：保护内存修改跟踪
公开(公告)号：US06981172B2
公开(公告)日：2005-12-27
申请号：US09938800
申请日：2001-08-24
申请人： Paul Jeffrey Garnett , Jeremy Graham Harris
发明人： Paul Jeffrey Garnett , Jeremy Graham Harris
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/2097 , G06F11/1032 , G06F11/1675
摘要： A dirty memory is operable to store dirty indicators, each dirty indicator being settable to a given value indicative that a page of memory associated therewith has been dirtied. The dirty indicators are stored in groups with each group having associated therewith a validity indicator computed from the dirty indicator values of the group. The control logic is operable on reading a group to compute a validity indicator value based on the dirty indicator values for the group to determine the integrity of the group. The integrity can be confirmed by comparing the computed validity indicator value to a validity indicator value read for the group. Where the value read and the value computed compare equal, it can be assumed that the dirty indicator values of the group are correct. Preferably the validity indicator is a parity indicator. Although parity does not provide for error correction, parity has the advantage that minimal overhead is needed for computation and storage. When a parity error is detected, all of the dirty indicators associated with the parity indicator that has flagged a potential error are treated as suspect. As a consequence, when a parity error is detected for a of dirty indicators, all of the pages of memory associated with those dirty indicators are treated as being dirtied and they are therefore copied between memories. The dirty indicators and the parity indicator are then reset.
摘要翻译：脏存储器可操作以存储脏指示器，每个脏指示器可设置为给定值，指示与其相关联的存储器页已被弄脏。脏指示符被分组地存储，每个组具有与其相关联的从组的脏指示符值计算的有效性指示符。控制逻辑在读取组时可操作以基于组的脏指示符值来计算有效性指示符值，以确定组的完整性。可以通过将计算的有效性指标值与组读取的有效性指标值进行比较来确认完整性。在读取值和计算值比较相等的情况下，可以假定组的脏指示符值正确。优选地，有效性指示符是奇偶校验指示符。虽然奇偶校验不提供纠错，但奇偶校验具有计算和存储所需的最小开销的优点。当检测到奇偶校验错误时，与标有潜在错误的奇偶校验指示符相关联的所有脏指示器被视为可疑。因此，当对于脏指示符检测到奇偶校验错误时，与这些脏指示符相关联的所有存储器页面被视为被弄脏并且因此被复制在存储器之间。脏指示器和奇偶校验指示器然后复位。

9. 发明授权

US07232332B2 Support and grounding structure 有权
标题翻译：支撑和接地结构
公开(公告)号：US07232332B2
公开(公告)日：2007-06-19
申请号：US10337500
申请日：2003-01-07
申请人： Jay Kevin Osborn , Paul Jeffrey Garnett , Graham Bestwick
发明人： Jay Kevin Osborn , Paul Jeffrey Garnett , Graham Bestwick
IPC分类号： H01R13/00
CPC分类号： H01L23/4006 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of a heat sink assembly are disclosed. In one embodiment, the heat sink assembly includes a processor mounted onto a circuit board; a heat sink located in thermal contact with the processor at the side of the processor opposite circuit board; and an electromagnetic shielding member located between the circuit board and the heat sink. The electromagnetic shielding member is releasably attached to the circuit board. Additionally, or in the alternative, the heat sink is biased toward the processor by a load spring and the electromagnetic shielding member is configured to provide a spring force between the circuit board and the heat sink, counter directional to the bias from the load spring.
摘要翻译：公开了散热器组件的各种实施例。在一个实施例中，散热器组件包括安装在电路板上的处理器; 散热器，位于与处理器相对的电路板处的处理器热接触; 以及位于电路板和散热器之间的电磁屏蔽构件。电磁屏蔽构件可释放地附接到电路板。另外，或者替代地，散热器通过负载弹簧被偏置到处理器，并且电磁屏蔽构件构造成在电路板和散热器之间提供与来自负载弹簧的偏压相反的弹簧力。

10. 发明授权

US06961826B2 Processor state reintegration using bridge direct memory access controller 有权
标题翻译：使用桥接器直接存储器访问控制器的处理器状态重新集成
公开(公告)号：US06961826B2
公开(公告)日：2005-11-01
申请号：US09939277
申请日：2001-08-24
申请人： Paul Jeffrey Garnett , Stephen Rowlinson , Jeremy Graham Harris
发明人： Paul Jeffrey Garnett , Stephen Rowlinson , Jeremy Graham Harris
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F11/1658 , G06F13/4027
摘要： A computer system comprising at least two processing sets. Each processing set includes main memory. A bridge connects the processing sets. At least a first processing set further including a dirty memory having dirty indicators for indicating dirtied blocks of the main memory of the first processing set. The bridge includes a direct memory access controller that is operable to copy blocks of the first processing set indicated in the dirty memory to the main memory of another processing set. The processors do not, therefore, need to carry out the copying, whereby the processor overhead associated therewith can be avoided, increasing the efficiency of memory reintegration. The direct memory access controller can be arranged to search the dirty memory for dirty indicators indicative of dirtied blocks. Alternatively, the dirty memory can include control logic operable to search the dirty memory for dirty indicators indicative of dirtied blocks. The direct memory access controller can be arranged to instigate a search of the dirty memory.
摘要翻译：一种包括至少两个处理集合的计算机系统。每个处理集包括主存储器。桥连接处理集。至少第一处理组还包括具有用于指示第一处理组的主存储器的脏块的脏指示器的脏存储器。该桥包括直接存储器访问控制器，其可操作以将在脏存储器中指示的第一处理集合的块复制到另一处理集合的主存储器。因此，处理器不需要执行复制，由此可以避免与其相关联的处理器开销，从而提高存储器重新集成的效率。直接存储器访问控制器可以被布置成在脏存储器中搜索指示污垢块的脏指示器。或者，脏存储器可以包括可操作以搜索脏存储器中的指示污垢块的脏指示器的控制逻辑。直接存储器访问控制器可被布置成发起对脏存储器的搜索。

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