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1. 发明申请

US20090265532A1 ANTI-PREFETCH INSTRUCTION 有权
标题翻译：防伪指示
公开(公告)号：US20090265532A1
公开(公告)日：2009-10-22
申请号：US12104159
申请日：2008-04-16
申请人： Paul Caprioli , Sherman H. Yip , Gideon Levinsky
发明人： Paul Caprioli , Sherman H. Yip , Gideon Levinsky
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F12/0862
摘要： Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.
摘要翻译：本发明的实施例执行反预取指令。这些实施例首先解码处理器中的解码单元中的指令，以准备执行指令。在对反预取指令进行解码时，这些实施例使解码单元停止以防止解码后续指令。这些实施例然后执行反预取指令，其中执行反预取指令涉及：（1）在L1高速缓存中发送用于高速缓存行的预取请求; （2）确定预取请求是否在L1高速缓存中命中; （3）如果预取请求命中在L1高速缓存中，则确定高速缓存线是否包含预定值; 以及（4）基于所述预提取请求是否在所述L1高速缓存中的命中或所述高速缓存行中的数据的值有条件地执行后续操作。

2. 发明授权

US08732438B2 Anti-prefetch instruction 有权
标题翻译：反预取指令
公开(公告)号：US08732438B2
公开(公告)日：2014-05-20
申请号：US12104159
申请日：2008-04-16
申请人： Paul Caprioli , Sherman H. Yip , Gideon N. Levinsky
发明人： Paul Caprioli , Sherman H. Yip , Gideon N. Levinsky
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F12/0862
摘要： Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.
摘要翻译：本发明的实施例执行反预取指令。这些实施例首先解码处理器中的解码单元中的指令，以准备执行指令。在对反预取指令进行解码时，这些实施例使解码单元停止以防止解码后续指令。这些实施例然后执行反预取指令，其中执行反预取指令涉及：（1）在L1高速缓存中发送用于高速缓存行的预取请求; （2）确定预取请求是否在L1高速缓存中命中; （3）如果预取请求命中在L1高速缓存中，则确定高速缓存线是否包含预定值; 以及（4）基于所述预提取请求是否在所述L1高速缓存中的命中或所述高速缓存行中的数据的值有条件地执行后续操作。

3. 发明授权

US08364900B2 Pseudo-LRU cache line replacement for a high-speed cache 有权
标题翻译：用于高速缓存的伪LRU高速缓存行替代
公开(公告)号：US08364900B2
公开(公告)日：2013-01-29
申请号：US12029889
申请日：2008-02-12
申请人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
发明人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
IPC分类号： G06F12/00
CPC分类号： G06F12/125 , G06F12/0864 , Y02D10/13
摘要： Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate indices using the two or more indices. The system then uses at least one of the two or more indices or the two or more intermediate indices to perform a lookup in one or more lookup tables, wherein the lookup returns a value which identifies a least-recently-used way. Next, the system replaces the entry in the least-recently-used way.
摘要翻译：本发明的实施例提供了一种在偏斜相关高速缓存中以最近最近使用的方式替换条目的系统。系统从接收缓存行地址开始。然后系统使用高速缓存行地址生成两个或多个索引。接下来，系统使用两个或更多个索引生成两个或更多个中间索引。然后，系统使用两个或更多个索引中的至少一个或两个或更多个中间索引来在一个或多个查找表中执行查找，其中查找返回标识最近最近使用的方式的值。接下来，系统以最近最少使用的方式替换条目。

4. 发明授权

US07418581B2 Method and apparatus for sampling instructions on a processor that supports speculative execution 有权
标题翻译：用于在支持推测性执行的处理器上对指令进行采样的方法和装置
公开(公告)号：US07418581B2
公开(公告)日：2008-08-26
申请号：US11405965
申请日：2006-04-17
申请人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip
发明人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip
IPC分类号： G06F9/30
CPC分类号： G06F11/3466 , G06F9/3842 , G06F9/3867
摘要： One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds deferred instructions which are deferred because of an unresolved data dependency. The system then records information about the selected instruction during execution of the selected instruction, whereby the recorded information can be used to determine the performance of the processor.
摘要翻译：本发明的一个实施例提供了一种在支持推测执行的处理器上对指令进行采样的系统。系统首先选择指令，其中选择指令涉及选择从指令获取单元或延迟队列接收的指令，其中延迟队列保存由于未解决的数据依赖性而延迟的延迟指令。然后，系统在执行所选择的指令期间记录关于所选指令的信息，由此可以使用所记录的信息来确定处理器的性能。

5. 发明申请

US20100299482A1 METHOD AND APPARATUS FOR DETERMINING CACHE STORAGE LOCATIONS BASED ON LATENCY REQUIREMENTS 有权
标题翻译：基于延迟要求确定缓存存储位置的方法和装置
公开(公告)号：US20100299482A1
公开(公告)日：2010-11-25
申请号：US12470639
申请日：2009-05-22
申请人： Gideon N. Levinsky , Paul Caprioli , Sherman H. Yip
发明人： Gideon N. Levinsky , Paul Caprioli , Sherman H. Yip
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/0864 , G06F12/1027 , G06F2212/271
摘要： A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.
摘要翻译：公开了一种用于以快速方式或缓存方式存储二进制信息的方法。该方法包括接收要存储在具有多个方式的高速缓冲存储器中的二进制信息块。多种方式包括方法的第一子集和方法的第二子集，其中来自第一方法子集之一的第一执行核心的高速缓存访问具有比来自第二子集的第二子集方法。该方法还包括基于预定访问等待时间和与二进制信息块相关联的一个或多个参数确定是否将二进制信息块存储为第一组方式之一或第二组路径之一。

6. 发明授权

US07757068B2 Method and apparatus for measuring performance during speculative execution 有权
标题翻译：用于在推测执行期间测量性能的方法和装置
公开(公告)号：US07757068B2
公开(公告)日：2010-07-13
申请号：US11654270
申请日：2007-01-16
申请人： Paul Caprioli , Shailender Chaudhry , Sherman H. Yip
发明人： Paul Caprioli , Shailender Chaudhry , Sherman H. Yip
IPC分类号： G06F7/38
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06F9/3863 , G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F11/348 , G06F2201/88 , G06F2201/885
摘要： One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the speculative-execution episode the system enables a speculative execution monitor. The system then uses the speculative execution monitor to monitor instructions during the speculative-execution episode to record data values relating to the speculative-execution episode. Upon returning to normal-execution mode, the system disables the speculative execution monitor. The data values recorded by the speculative execution monitor facilitate measuring processor performance during speculative execution.
摘要翻译：本发明的一个实施例提供了一种用于在推测执行期间测量处理器性能的系统。系统通过在正常执行模式下执行指令来启动。然后，系统进入推测执行情节，其中指令被推测地执行而不被提交到处理器的架构状态。在进入推测执行情节时，系统启用推测执行监视器。然后，系统使用推测执行监视器在推测执行情节期间监视指令，以记录与推测执行情节相关的数据值。返回到正常执行模式后，系统将禁用推测执行监视器。由推测执行监视器记录的数据值有助于在推测执行期间测量处理器的性能。

7. 发明授权

US07610474B2 Mechanism for hardware tracking of return address after tail call elimination of return-type instruction 有权
标题翻译：尾部呼叫消除返回类型指令后返回地址的硬件跟踪机制
公开(公告)号：US07610474B2
公开(公告)日：2009-10-27
申请号：US11352147
申请日：2006-02-10
申请人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
发明人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3842 , G06F9/3861
摘要： A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one embodiment of the invention, an apparatus includes a processor pipeline and at least a first return address stack for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline. The processor pipeline is configured to maintain the first return address stack unchanged in response to detection of a tail-call elimination sequence of one or more instructions associated with a first call-type instruction encountered by the first stage. The processor pipeline is configured to push a return address associated with the first call-type instruction onto the first return address stack otherwise.
摘要翻译：检测到返回类型指令的尾部消除消息后，技术维护返回地址堆栈（RAS）内容和RAS顶层（TOS）指针的对齐。在本发明的至少一个实施例中，一种装置包括处理器流水线和至少第一返回地址堆栈，用于在处理器流水线的第一级保持与指令流相关联的返回地址堆栈。响应于检测到与第一级遇到的第一呼叫类型指令相关联的一个或多个指令的尾部呼叫消除序列，处理器流水线被配置为维持第一返回地址堆栈不变。否则处理器流水线被配置为将与第一调用类型指令相关联的返回地址推送到第一返回地址堆栈。

8. 发明申请

US20090254905A1 FACILITATING TRANSACTIONAL EXECUTION IN A PROCESSOR THAT SUPPORTS SIMULTANEOUS SPECULATIVE THREADING 有权
标题翻译：在支持同时进行线性加工的处理器中促进交易执行
公开(公告)号：US20090254905A1
公开(公告)日：2009-10-08
申请号：US12061554
申请日：2008-04-02
申请人： Sherman H. Yip , Paul Caprioli , Marc Tremblay
发明人： Sherman H. Yip , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/3842 , G06F9/3851 , G06F12/0842
摘要： Embodiments of the present invention provide a system that executes a transaction on a simultaneous speculative threading (SST) processor. In these embodiments, the processor includes a primary strand and a subordinate strand. Upon encountering a transaction with the primary strand while executing instructions non-transactionally, the processor checkpoints the primary strand and executes the transaction with the primary strand while continuing to non-transactionally execute deferred instructions with the subordinate strand. When the subordinate strand non-transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate the first strand ID. When the primary strand transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate a second strand ID.
摘要翻译：本发明的实施例提供了一种在同时推测的线程（SST）处理器上执行交易的系统。在这些实施例中，处理器包括主链和从属链。在非事务性地执行指令的同时遇到与主链的事务时，处理器检查主链，并与主链一起执行事务，同时继续非事务地执行与下级链的延迟指令。当下级链在事务期间非事务地访问高速缓存行时，处理器更新用于高速缓存行的记录以指示第一个链ID。当主链在事务期间事务地访问高速缓存行时，处理器更新用于高速缓存行的记录以指示第二个链ID。

9. 发明授权

US07480787B1 Method and structure for pipelining of SIMD conditional moves 有权
标题翻译： SIMD条件移动流水线的方法和结构
公开(公告)号：US07480787B1
公开(公告)日：2009-01-20
申请号：US11341001
申请日：2006-01-27
申请人： Paul Caprioli , Lawrence A. Spracklen , Sherman H. Yip
发明人： Paul Caprioli , Lawrence A. Spracklen , Sherman H. Yip
IPC分类号： G06F9/00
CPC分类号： G06F9/3885 , G06F9/3001 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/3887
摘要： A mask is first generated in a general-purpose integer register. The mask is generated by executing a single instruction multiple data (SIMD) instruction on a plurality of operands stored in a plurality of registers and by writing the result to the general-purpose integer register. Next, a conditional-move mask is generated in a register using the mask, and then the conditional-move mask is used in selecting operands from the plurality of operands to generate a result in another register.
摘要翻译：首先在通用整数寄存器中生成掩码。通过对存储在多个寄存器中的多个操作数执行单指令多数据（SIMD）指令并将结果写入通用整数寄存器来生成掩码。接下来，使用掩码在寄存器中生成条件移动掩码，然后使用条件移动掩码来选择来自多个操作数的操作数，以在另一个寄存器中生成结果。

10. 发明授权

US07461208B1 Circuitry and method for accessing an associative cache with parallel determination of data and data availability 有权
标题翻译：用于通过并行确定数据和数据可用性访问关联高速缓存的电路和方法
公开(公告)号：US07461208B1
公开(公告)日：2008-12-02
申请号：US11155147
申请日：2005-06-16
申请人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
发明人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
IPC分类号： G06F13/16
CPC分类号： G06F12/0864 , G06F2212/1016 , G06F2212/6082
摘要： A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict. The circuit further includes a memory in communication with the data selection circuitry and the outcome parallel processing circuit. The memory is configured to store a bank select table, whereby the bank select table is configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data. Methods for accessing the associative cache are also described.
摘要翻译：提供了一种用于访问关联高速缓存的电路。电路包括与关联高速缓存通信的数据选择电路和结果并行处理电路。结果并行处理电路被配置为确定来自关联高速缓存的数据的访问是否是高速缓存命中，高速缓存未命中或高速缓存错误预测中的一个。电路还包括与数据选择电路和结果并行处理电路通信的存储器。存储器被配置为存储存储体选择表，由此存储体选择表被配置为包括定义从其输出数据的关联高速缓存的多个存储区之一的选择的条目。还描述了访问关联高速缓存的方法。

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