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1. 发明授权

US06542539B1 Multiported register file for coefficient use in filters 失效
标题翻译：滤波器中系数使用的多位寄存器文件
公开(公告)号：US06542539B1
公开(公告)日：2003-04-01
申请号：US08996868
申请日：1997-12-23
申请人： Patrik Larsson , Christopher John Nicol
发明人： Patrik Larsson , Christopher John Nicol
IPC分类号： H03H740
CPC分类号： H03H21/0012
摘要： Multiported register files for use in storing coefficients in adaptive FIR filters. incorporate computational ability, e.g., the ability to perform computation on coefficient values or derivatives thereof, or to control the operations performed thereon. For example, a multiported register file may incorporate an overflow/underflow detection and/or saturation unit. Also, the multiported register file may incorporate a special encoder to speed up the multiplication process, e.g., the so-called “Booth” encoder. Likewise, the multiported register file may incorporate a converter for changing the representation of the coefficients, e.g., a two's complement to sign-magnitude converter. All computation performed in the multiported register file is performed outside of the critical path of the filtering or of the coefficient updating. Using such improved multiported register files, adaptive FIR filters can be constructed which operate faster, and with lower power consumption.
摘要翻译：用于在自适应FIR滤波器中存储系数的多端口寄存器文件。结合计算能力，例如对系数值或其派生词进行计算的能力，或控制其上执行的操作。例如，多端口寄存器文件可以包含溢出/下溢检测和/或饱和单元。此外，多端口寄存器文件可以包含特殊编码器以加速乘法过程，例如所谓的“Booth”编码器。类似地，多端口寄存器堆可以包括用于改变系数的表示的转换器，例如二进制符号幅度转换器的补码。在多端口寄存器文件中执行的所有计算都在滤波或系数更新的关键路径之外执行。使用这种改进的多端口寄存器文件，可以构建自适应FIR滤波器，其运行更快，功耗更低。

2. 发明授权

US06452987B1 Fast start-up in discrete multi-tone (DMT) based communications system 失效
标题翻译：基于离散多音（DMT）通信系统的快速启动
公开(公告)号：US06452987B1
公开(公告)日：2002-09-17
申请号：US09199775
申请日：1998-11-25
申请人： Patrik Larsson , Jean-Jacques Werner , Jian Yang
发明人： Patrik Larsson , Jean-Jacques Werner , Jian Yang
IPC分类号： H04L2708
CPC分类号： H04L27/2647 , H04L25/03159 , H04L27/2614 , H04L2025/03414 , H04L2025/03522
摘要： In an Asymmetric Digital Subscriber Loop (ADSL) Discrete Multi-Tone (DMT) system, a DMT receiver uses, during start-up, an automatic gain control (AGC) element and a rotator element in place of a one-tap complex finite impulse response (FIR) filter.
摘要翻译：在非对称数字用户环路（ADSL）离散多音（DMT）系统中，DMT接收机在启动期间使用自动增益控制（AGC）元件和旋转元件来代替单抽头复数有限脉冲响应（FIR）过滤器。

3. 发明授权

US06344772B1 Apparatus and method for capacitance multiplication 有权
标题翻译：电容倍增装置及方法
公开(公告)号：US06344772B1
公开(公告)日：2002-02-05
申请号：US09587950
申请日：2000-06-06
申请人： Patrik Larsson
发明人： Patrik Larsson
IPC分类号： H03B100
CPC分类号： H03L7/0891 , H03H11/405 , H03L7/093
摘要： A capacitance multiplier network embodying the invention includes a first resistor, R1, connected between a first node and an intermediate node and a first capacitor, C1, connected between the intermediate node and a point of reference potential. A unity gain amplifier has an input connected to the intermediate node and its output is connected via a second resistor, R2, to the first node. The unity gain amplifier ensures that the voltage drop across the second resistor is equal to the voltage drop across the first resistor. The effective capacitance, Ce, of the network is equal to C1 times [R1+R2]/R2. Thus, by making R1 larger than R2, Ce is much large than the capacitance of C1. The capacitance multiplier network is well suited for use in phase locked loop circuits and enables the integration of a very dense circuit on the same IC chip.
摘要翻译：体现本发明的电容倍增器网络包括连接在第一节点和中间节点之间的第一电阻器R1和连接在中间节点和参考电位之间的第一电容器C1。单位增益放大器具有连接到中间节点的输入，并且其输出经由第二电阻器R2连接到第一节点。单位增益放大器确保了第二个电阻上的电压降等于第一个电阻上的电压降。网络的有效电容Ce等于C1倍[R1 + R2] / R2。因此，通过使R1大于R2，Ce比C1的电容大得多。电容倍增器网络非常适合用于锁相环电路，并且能够将非常密集的电路集成在同一个IC芯片上。

4. 发明授权

US6163184A Phase locked loop (PLL) circuit 有权
标题翻译：锁相环（PLL）电路
公开(公告)号：US6163184A
公开(公告)日：2000-12-19
申请号：US208524
申请日：1998-12-09
申请人： Patrik Larsson
发明人： Patrik Larsson
IPC分类号： H03L7/089 , H03L7/093 , H03L7/099 , H03L7/183 , H03L7/06
CPC分类号： H03L7/183 , H03L7/0898 , H03L7/093 , H03L7/0995
摘要： A phase locked loop (PLL) includes a programmable frequency multiplier section and a programmable divide-by-N network connected in a feedback loop between an output and an input of the frequency multiplier. The frequency multiplier section includes programmable circuitry which is programmed to vary as a function of N to render the bandwidth of the PLL independent of the divider ratio "N". The frequency multiplier includes a charge pump circuit, a filter circuit and a voltage controlled oscillator (VCO) circuit with the programmable circuitry being formed in one of these circuits to render the bandwidth of the PLL independent of the divider ratio, whereby the bandwidth is increased and the jitter at the PLL output is decreased.
摘要翻译：锁相环（PLL）包括连接在倍频器的输出端和输入端之间的反馈环路中的可编程分频器N和可编程分频网络。倍频器部分包括可编程电路，其被编程为根据N的函数而变化，以使PLL的带宽与分频比“N”无关。倍频器包括电荷泵电路，滤波器电路和压控振荡器（VCO）电路，其中可编程电路形成在这些电路之一中，以使得PLL的带宽与分频比无关，从而带宽增加并且PLL输出端的抖动减小。

5. 发明授权

US6157694A Fractional frequency divider 有权
标题翻译：分数分频器
公开(公告)号：US6157694A
公开(公告)日：2000-12-05
申请号：US208299
申请日：1998-12-09
申请人： Patrik Larsson
发明人： Patrik Larsson
IPC分类号： H03K23/68 , H03L7/099 , H03L7/18 , H03L7/197 , H03K21/00
CPC分类号： H03K23/68 , H03L7/0996 , H03L7/18 , H03L7/1974
摘要： In systems embodying the invention X clock signals having the same frequency, with each clock signal having a different phase, are supplied to the inputs of a multiplexer whose output is connected to the input of an "integer" frequency divider circuit; where X is an integer greater than 1. The mulitplexer is controlled to selectively supply different ones of the X clock signals to the frequency divider circuit for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit.
摘要翻译：在体现本发明的系统中，每个时钟信号具有不同相位的具有相同频率的X个时钟信号被提供给多路复用器的输入端，其输出端连接到“整数”分频器电路的输入端; 其中X是大于1的整数。多路复用器被控制以选择性地将不同的X时钟信号提供给分频器电路，用于在分频器电路的输出端产生频率是分频比的函数的信号分频器电路和提供给分频器电路的时钟信号的顺序。

6. 发明授权

US10071632B2 Electrical system for a vehicle with start/stop 有权
公开(公告)号：US10071632B2
公开(公告)日：2018-09-11
申请号：US13593124
申请日：2012-08-23
申请人： Torbjoern Larsson , Patrik Larsson , Daniel Midholm , Fredrik Ulmhage
发明人： Torbjoern Larsson , Patrik Larsson , Daniel Midholm , Fredrik Ulmhage
IPC分类号： B60L1/00 , F02N11/08 , H02J7/14
CPC分类号： B60L1/00 , F02N11/0814 , F02N11/0866 , H02J7/1423 , Y02T10/48 , Y02T10/7005
摘要： An electrical system for a vehicle having an internal combustion engine provided with a start/stop system includes a primary battery connectible to an engine starter motor, an alternator and an electrical load in parallel with one another and selectively connectible in parallel with the primary battery via a first switch, and a third source of electrical energy selectively connectible in parallel with the alternator via a second switch. A DC/DC converter may be arranged in parallel with the alternator for selectively charging the third source of electrical energy via the second switch. A secondary battery may be arranged in parallel with the alternator.

7. 发明授权

US09475482B2 Plug-in hybrid electric vehicle 有权
标题翻译：插电式混合动力电动车
公开(公告)号：US09475482B2
公开(公告)日：2016-10-25
申请号：US13609990
申请日：2012-09-11
申请人： Klas Niste , Robert Eriksson , Patrik Larsson
发明人： Klas Niste , Robert Eriksson , Patrik Larsson
IPC分类号： B60W10/26 , B60W20/00 , B60K6/28 , B60W50/023 , B60K6/485 , B60K6/52 , B60W10/06 , B60W10/08 , B60L11/18 , H02J7/14
CPC分类号： B60L3/0092 , B60K6/28 , B60K6/485 , B60K6/52 , B60L3/0046 , B60L3/04 , B60L11/1868 , B60W10/06 , B60W10/08 , B60W10/26 , B60W20/00 , B60W20/50 , B60W50/023 , B60W2510/244 , B60W2540/10 , H02J7/1423 , Y02T10/6226 , Y02T10/6265 , Y02T10/6269 , Y02T10/6278 , Y02T10/6286 , Y02T10/646 , Y02T10/7005 , Y02T10/7066
摘要： A plug-in hybrid electric vehicle includes an internal combustion engine driving a pair of wheels on a first axle and a transmission drivingly connecting the internal combustion engine and the wheels on a first axle. An integrated starter-generator is mounted on the internal combustion engine crankshaft between said internal combustion engine and the transmission. The vehicle further includes an electric motor driving a pair of wheels on a first axle and a main battery pack connected to a further electric motor arranged to supply electric power for driving the wheels on a second axle. The electric drive means can comprise one electric motor driving the second axle via a differential, two electric motors each driving one half of the second axle or two electric wheel motors for the respective wheels on the second axle. An additional battery is connected to the integrated starter-generator for starting the engine.
摘要翻译：插电式混合动力电动车辆包括驱动第一车轴上的一对车轮的内燃机和在第一车轴上驱动地连接内燃机和车轮的变速器。在内燃机与变速器之间的内燃机曲轴上安装有集成起动发电机。车辆还包括驱动第一轴上的一对车轮的电动马达和连接到另外的电动马达的主电池组，该另一个电动机被布置成在第二轴上提供用于驱动车轮的电力。电驱动装置可以包括一个电动马达，它通过差速器驱动第二轴，两个电动机分别驱动第二轴的一半，或两个电动轮马达用于第二轴上的各个车轮。一个额外的电池连接到集成起动发电机起动发动机。

8. 发明申请

US20130229049A1 ELECTRICAL SYSTEM FOR A VEHICLE WITH START/STOP 审中-公开
标题翻译：用于起动/停止的车辆的电气系统
公开(公告)号：US20130229049A1
公开(公告)日：2013-09-05
申请号：US13593124
申请日：2012-08-23
申请人： Torbjoern Larsson , Patrik Larsson , Daniel Midholm , Fredrik Ulmhage
发明人： Torbjoern Larsson , Patrik Larsson , Daniel Midholm , Fredrik Ulmhage
IPC分类号： B60L1/00
CPC分类号： B60L1/00 , F02N11/0814 , F02N11/0866 , H02J7/1423 , Y02T10/48 , Y02T10/7005
摘要： An electrical system for a vehicle having an internal combustion engine provided with a start/stop system includes a primary battery connectible to an engine starter motor, an alternator and an electrical load in parallel with one another and selectively connectible in parallel with the primary battery via a first switch, and a third source of electrical energy selectively connectible in parallel with the alternator via a second switch. A DC/DC converter may be arranged in parallel with the alternator for selectively charging the third source of electrical energy via the second switch. A secondary battery may be arranged in parallel with the alternator.
摘要翻译：具有设置有起动/停止系统的内燃机的车辆的电气系统包括可连接到发动机起动电动机，交流发电机和彼此并联的电负载的一次电池，并且可与主电池经由第一开关和第三电能源通过第二开关与交流发电机并联选择性地连接。 DC / DC转换器可以与交流发电机并联布置，用于经由第二开关选择性地对第三电源进行充电。二次电池可以与交流发电机并联布置。

9. 发明授权

US06687722B1 High-speed/low power finite impulse response filter 失效
标题翻译：高速/低功耗有限脉冲响应滤波器
公开(公告)号：US06687722B1
公开(公告)日：2004-02-03
申请号：US09526836
申请日：2000-03-16
申请人： Patrik Larsson , Christopher John Nicol
发明人： Patrik Larsson , Christopher John Nicol
IPC分类号： G06F1710
CPC分类号： H03H17/06
摘要： A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the load on the clock can be reduced, thereby achieving reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder. The combination of a reduction of half of the flip-flops and a replacement of a simpler carry-save adder for each of the carry-save adders results in a significant improvement in the overall filter performance and power and space consumption.
摘要翻译：有限脉冲响应滤波器输出表示采用部分进位保存格式，从而减少了多个触发器，从而减少了功率。通过用组合的进位保存加法器和进位传播加法器替代有限脉冲响应滤波器的输出侧上的最低有效位处理部分，后跟寄存器而不是两个触发器，可以减少时钟上的负载，从而实现减少的传播延迟。为了进一步提高有限脉冲响应滤波器的性能，在最低有效位部分采用了更简单的进位保存加法器，这是可能的，这是由于在每个进位存储加法器的输入端使用单个寄存器，比两个触发器，一个用于进位输出，一个用于从加法器输出的和。减少一半的触发器和用于每个进位保存加法器的更简单的进位保存加法器的组合导致整体滤波器性能和功率和空间消耗的显着改善。

10. 发明授权

US06310498B1 Digital phase selection circuitry and method for reducing jitter 有权
标题翻译：数字相位选择电路和减少抖动的方法
公开(公告)号：US06310498B1
公开(公告)日：2001-10-30
申请号：US09208523
申请日：1998-12-09
申请人： Patrik Larsson
发明人： Patrik Larsson
IPC分类号： H03L700
CPC分类号： H03L7/18 , H03K5/133 , H03L7/0891 , H03L7/0996 , H04L7/0337
摘要： In systems embodying the invention a voltage responsive circuit is used to generate a number of different clock signals having the same frequency, with each clock signal being delayed relative to any other clock signal by a certain delay which is a function of the amplitude of a control voltage applied to the voltage responsive circuit. The clock signals are multiplexed to enable any one of the different clock signals to be selected and to then be compared with a reference frequency signal for producing a gradually varying control voltage which is applied to the voltage responsive circuit. The different clock signals are suited for use in applications such as clock recovery and frequency synthesizer systems, where very little jitter is desired.
摘要翻译：在体现本发明的系统中，电压响应电路用于产生具有相同频率的多个不同的时钟信号，每个时钟信号相对于任何其它时钟信号被延迟一定的延迟，该延迟是控制幅度的函数施加到电压响应电路的电压。时钟信号被复用以使得可以选择不同的时钟信号中的任意一个，然后将其与参考频率信号进行比较，以产生施加到电压响应电路的逐渐变化的控制电压。不同的时钟信号适用于诸如时钟恢复和频率合成器系统的应用，其中需要很少的抖动。

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