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1. 发明授权

US5629630A Semiconductor wafer contact system and method for contacting a semiconductor wafer 失效
标题翻译：用于接触半导体晶片的半导体晶片接触系统和方法
公开(公告)号：US5629630A
公开(公告)日：1997-05-13
申请号：US395127
申请日：1995-02-27
申请人： Patrick F. Thompson , William M. Williams , Scott E. Lindsey , Barbara Vasquez
发明人： Patrick F. Thompson , William M. Williams , Scott E. Lindsey , Barbara Vasquez
IPC分类号： G01R1/06 , G01R1/073 , G01R31/28 , H01L21/66
CPC分类号： G01R1/07314 , G01R31/2831
摘要： A semiconductor wafer contact system includes a base substrate (13) which has an array of raised supports (18). The array of raised supports (18) are distributed in a pattern corresponding to the pattern of electrical contacts (12) on the semiconductor wafer (10), to be contacted. In between the base substrate (13) and the wafer to be contacted (10) is a flexible circuit layer (14) including an array of electrical contacts (15) having the same pattern as the contacts (12) of the wafer and the raised supports (18). The raised supports (18) provide focused and localized force, pressing the membrane test contacts (15) against the wafer electrical contacts (12).
摘要翻译：半导体晶片接触系统包括具有升高的支撑件（18）阵列的基底（13）。凸起支撑件（18）的阵列以对应于半导体晶片（10）上的电触点（12）的图案的图案分布，以被接触。在基底基板（13）和待接触晶片（10）之间的是柔性电路层（14），其包括具有与晶片的触点（12）相同图案的电触头阵列（15），并且凸起支持（18）。凸起的支撑件（18）提供聚焦和局部的力，将膜测试触点（15）压在晶片电触头（12）上。

2. 发明授权

US5773986A Semiconductor wafer contact system and method for contacting a semiconductor wafer 失效
标题翻译：用于接触半导体晶片的半导体晶片接触系统和方法
公开(公告)号：US5773986A
公开(公告)日：1998-06-30
申请号：US416121
申请日：1995-04-03
申请人： Patrick F. Thompson , William M. Williams , Scott E. Lindsey , Barbara Vasquez
发明人： Patrick F. Thompson , William M. Williams , Scott E. Lindsey , Barbara Vasquez
IPC分类号： G01R31/28 , G01R1/073
CPC分类号： G01R31/2886 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01078
摘要： A semiconductor wafer contact system includes a sealed bladder (32) containing incompressible material. The sealed bladder (32) presses against a flexible circuit layer (28) including an array of electrical contacts (30). The bladder (32) forces the array of electrical contacts (30) against a corresponding array of device electrical contacts (12) on die (11) of a semiconductor wafer (10). The bladder (32) adapts in shape to compensate for die level and wafer level irregularities in contact height and non-parallelism. Additionally, bladder (32) ensures a constant force between membrane contacts (30) and die contacts (12), across the entire wafer (10).
摘要翻译：半导体晶片接触系统包括含有不可压缩材料的密封囊（32）。密封的囊（32）压靠包括电触头阵列（30）的柔性电路层（28）。气囊（32）迫使电触点阵列抵靠在半导体晶片（10）的芯片（11）上的相应阵列的器件电触点（12）。囊（32）的形状适应于补偿接触高度和非平行度下的晶片级和晶片级不规则性。另外，囊（32）确保膜接触件（30）和管芯接触件（12）之间跨越整个晶片（10）的恒定的力。

3. 发明授权

US5602491A Integrated circuit testing board having constrained thermal expansion characteristics 失效
标题翻译：集成电路测试板具有受限的热膨胀特性
公开(公告)号：US5602491A
公开(公告)日：1997-02-11
申请号：US405317
申请日：1995-03-16
申请人： Barbara Vasquez , John W. Stafford , William M. Williams
发明人： Barbara Vasquez , John W. Stafford , William M. Williams
IPC分类号： G01R31/26 , G01R1/073 , G01R31/28 , H01L21/66 , H01L23/373 , H05K3/42 , H05K3/46 , G01R31/02
CPC分类号： G01R31/2863 , G01R1/07314 , H01L23/3735 , H01L23/3737 , H05K3/4641 , H01L2924/0002 , H05K2201/015 , H05K2201/0209 , H05K2201/068 , H05K3/429 , H05K3/4611
摘要： A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12). One or more constraint layers (18,20) are disposed in the dielectric material, and the constraint layers have a coefficient of thermal expansion of about 1-6 ppm/.degree.C. In a preferred embodiment, the dielectric material is a fluoropolymer with-a ceramic or silica filler, and the constraint layers are an iron-nickel alloy of about 30-40 percent nickel by weight. The board has thermal expansion characteristics substantially similar to silicon to ensure good contact to a silicon wafer during burn-in testing.
摘要翻译：一种用于测试设置在半导体晶片上的集成电路的板（10）。电路板包含多个基本上平行的信号层（14）和电源层（16），其被电介质材料（12）支撑并电隔离。一个或多个约束层（18,20）设置在电介质材料中，并且约束层的热膨胀系数为约1-6ppm /℃。在优选实施例中，电介质材料是含氟聚合物，陶瓷或二氧化硅填料，约束层是约30-40重量％镍的铁镍合金。该板具有基本上类似于硅的热膨胀特性，以确保在老化测试期间与硅晶片的良好接触。

4. 发明授权

US5556808A Method for aligning a semiconductor device 失效
标题翻译：半导体器件对准方法
公开(公告)号：US5556808A
公开(公告)日：1996-09-17
申请号：US268986
申请日：1994-06-30
申请人： William M. Williams , Barbara Vasquez , Marlene J. Begay , Patrick Thompson
发明人： William M. Williams , Barbara Vasquez , Marlene J. Begay , Patrick Thompson
IPC分类号： H01L21/58 , H01L29/06 , H01L21/60
CPC分类号： H01L24/83 , H01L24/32 , H01L29/0657 , H01L2224/32057 , H01L2224/83136 , H01L2224/8319 , H01L2224/83385 , H01L2224/8385 , H01L2924/01039 , H01L2924/01078 , H01L2924/07802 , H01L2924/10158 , Y10S438/975
摘要： A system and method for aligning a semiconductor device (10) to a fixture (11) is provided. A first physical alignment feature (12) on the semiconductor device (10) and a second physical alignment (24) on the fixture (11) mate to align and hold the semiconductor device (10) in place. In one embodiment the physical alignment features (12) and (24) are produced using standard photolithography techniques, resulting in precise alignment features. In another embodiment the physical alignment features (12) and (24) are designed and placed to control the direction the thermal expansion of the semiconductor device (10) relative to the fixture (11).
摘要翻译：提供了一种用于将半导体器件（10）对准固定器（11）的系统和方法。半导体器件（10）上的第一物理对准特征（12）和固定装置（11）上的第二物理对准（24）配合以将半导体器件（10）对准和保持就位。在一个实施例中，使用标准光刻技术产生物理对准特征（12）和（24），导致精确对准特征。在另一个实施例中，物理对准特征（12）和（24）被设计和放置以控制半导体器件（10）相对于固定装置（11）的热膨胀的方向。

5. 发明授权

US06937047B2 Integrated circuit with test pad structure and method of testing 有权
标题翻译：具有测试板结构的集成电路和测试方法
公开(公告)号：US06937047B2
公开(公告)日：2005-08-30
申请号：US10634484
申请日：2003-08-05
申请人： Tu-Anh Tran , Richard K. Eguchi , Peter R. Harper , Chu-Chung Lee , William M. Williams , Lois Yong
发明人： Tu-Anh Tran , Richard K. Eguchi , Peter R. Harper , Chu-Chung Lee , William M. Williams , Lois Yong
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3187 , G11C29/48 , G01R31/02
CPC分类号： G11C29/1201 , G01R31/2884 , G01R31/31715 , G01R31/3187 , G11C29/48 , H01L2224/05554
摘要： A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.
摘要翻译：半导体器件在外围具有大量用于引线键合的接合焊盘。该半导体器件具有模块以及其他电路，但该模块比其他电路需要更长的测试时间。由于至少部分地由具有内置自检（BIST）电路的半导体器件，模块测试需要相对较少数量的接合焊盘（模块接合焊盘）。这些模块接合焊盘的功能在半导体器件的顶表面和内部复制，模块测试焊盘明显大于外围的焊盘。具有大的测试垫可以延长探针，从而提高并行测试能力。通过测试接口接口实现复制功能，使得模块接合焊盘和模块测试焊盘不必一起短路。

6. 发明授权

US4235590A Tinted UV cured coatings for photoflash lamps 失效
标题翻译：用于闪光灯的有色UV固化涂层
公开(公告)号：US4235590A
公开(公告)日：1980-11-25
申请号：US972196
申请日：1978-12-22
申请人： John E. Tozier , John W. Shaffer , William M. Williams
发明人： John E. Tozier , John W. Shaffer , William M. Williams
IPC分类号： G03B15/04 , F21K5/08 , F21K5/12 , F21K5/00 , F21K5/02
CPC分类号： F21K5/02
摘要： For use in a color-corrected photoflash unit, a flashlamp having a clear glass envelope with a transparent protective exterior coating comprising a UV curable photopolymer tinted with a colorant providing a portion of the total color correction capability of the unit.
摘要翻译：为了用于彩色校正的闪光灯单元中，具有透明保护性外部涂层的透明玻璃外壳的闪光灯，其包含着色剂，该着色剂具有着色剂，该着色剂提供该单元的总颜色校正能力的一部分。

7. 发明授权

US5330919A Method for electrically testing a semiconductor die using a test apparatus having an independent conductive plane 失效
标题翻译：使用具有独立导电平面的测试装置对半导体管芯进行电测试的方法
公开(公告)号：US5330919A
公开(公告)日：1994-07-19
申请号：US14591
申请日：1993-02-08
申请人： Gregory L. Westbrook , William M. Williams
发明人： Gregory L. Westbrook , William M. Williams
IPC分类号： G01R1/04 , H01L21/66 , H01L23/58 , G01R31/26
CPC分类号： H01L22/20 , G01R1/04 , H01L22/32 , H01L24/50 , H01L2924/14 , H01L2924/3011 , Y10T29/49004
摘要： A method for controlling a characteristic impedance during testing of a semiconductor die (13). The semiconductor die (13) is mounted in a TAB package (10 or 54 ) wherein the TAB package ( 10 or 54 ) lacks a ground plane. A conductive plate (40 or 70) is removably mounted to a test contact fixture ( 29 or 60 ) . The conductive plate (40 or 70) may be coated with a layer of dielectric material (50, 56, or 74) having a specified thickness. The layer of dielectric material (50, 56, or 74) contacts a plurality of conductive fingers (16). A microstrip transmission line is formed which includes the plurality of conductive fingers (16) , the layer of dielectric material (50, 56, or 74), and the conductive plate (40 or 70). The semiconductor die (13) is tested by a computer controlled automatic tester (28).
摘要翻译：一种用于在半导体管芯（13）的测试期间控制特性阻抗的方法。半导体管芯（13）安装在TAB封装（10或54）中，其中TAB封装（10或54）缺少接地层。导电板（40或70）可拆卸地安装到测试接触固定装置（29或60）上。导电板（40或70）可以涂覆有具有指定厚度的介电材料层（50,56或74）。介电材料层（50,56或74）接触多个导电指状物（16）。形成微带传输线，其包括多个导电指状物（16），介电材料层（50,56或74）和导电板（40或70）。半导体管芯（13）由计算机控制的自动测试器（28）测试。

8. 发明授权

US5087877A Test contact fixture using flexible circuit tape 失效
标题翻译：使用柔性电路胶带测试接触夹具
公开(公告)号：US5087877A
公开(公告)日：1992-02-11
申请号：US659644
申请日：1991-02-25
申请人： Dieter Frentz , Gregory L. Westbrook , William M. Williams
发明人： Dieter Frentz , Gregory L. Westbrook , William M. Williams
IPC分类号： G01R1/04
CPC分类号： G01R1/0433
摘要： A test contact fixture which uses a flexible printed circuit tape to make contact to the integrated circuit and to a rigid printed circuit board which is part of the test equipment. The flexible printed circuit tape is held tightly against a hardened steel support allowing extremely accurate alignment both horizontally and vertically. The mounting plate provides a ground plane so that each lead may easily be configured as a 50 ohm transmission line. Leads of the integrated circuit under test are held in contact with the conductive lines on top of the flexible printed circuit tape by externally applied pressure allowing extremely rapid loading and unloading of the fixture. The body of the integrated circuit is held clear of the contact surfaces allowing heat control fixtures to be used to control the temperature of the integrated circuit during testing.
摘要翻译：使用柔性印刷电路胶带与集成电路接触的测试接触夹具和作为测试设备一部分的刚性印刷电路板。柔性印刷电路胶带紧紧地保持在硬化钢支架上，从而水平和垂直地进行非常准确的对准。安装板提供接地平面，使得每个引线可以容易地配置为50欧姆的传输线。被测集成电路的引线通过外部施加的压力保持与柔性印刷电路胶带顶部的导电线接触，从而极大地加载和卸载固定装置。集成电路的主体保持远离接触表面，允许热控制夹具在测试期间用于控制集成电路的温度。

9. 发明授权

US4595427A Annealing process control method and apparatus 失效
标题翻译：退火过程控制方法和装置
公开(公告)号：US4595427A
公开(公告)日：1986-06-17
申请号：US663410
申请日：1984-10-22
申请人： Robin A. L. Drew , Wilson B. Muir , William M. Williams
发明人： Robin A. L. Drew , Wilson B. Muir , William M. Williams
IPC分类号： C21D11/00 , G05D23/19
CPC分类号： G05D23/1934 , C21D11/00
摘要： A method and an arrangement for following and controlling the progress of heat treatment of cold worked metals in an annealing furnace uses the changing electrical resistivity of the cold worked metal during the annealing process as a process control parameter. A sample of the cold worked metal is placed in a slave furnace along with a sample of the cold worked metal which has been previously annealed. The temperature of the slave furnace is controlled to follow and duplicate the temperature at any point of interest in the annealing furnace, and the differential resistivity between the two samples is measured to follow and control the progress of annealing.
摘要翻译：用于跟踪和控制退火炉中冷加工金属的热处理进展的方法和装置使用在退火过程期间冷加工金属的改变的电阻率作为过程控制参数。将冷加工金属的样品与预先退火的冷加工金属样品一起放置在从炉中。控制从炉的温度跟随并复制退火炉中任何感兴趣点处的温度，并测量两个样品之间的微分电阻率以跟随并控制退火的进行。

10. 发明授权

US5661042A Process for electrically connecting electrical devices using a conductive anisotropic material 失效
标题翻译：使用导电各向异性材料电气连接电气装置的方法
公开(公告)号：US5661042A
公开(公告)日：1997-08-26
申请号：US520118
申请日：1995-08-28
申请人： Treliant Fang , Lih-Tyng Hwang , William M. Williams
发明人： Treliant Fang , Lih-Tyng Hwang , William M. Williams
IPC分类号： G01R1/073 , G01R31/28 , H01L21/68 , H05K3/32 , H01L21/288 , H01L21/58 , H01L21/60
CPC分类号： H01L21/6835 , G01R1/073 , G01R31/2863 , H01L2224/16 , H01L2924/01079 , H05K3/323
摘要： A process for using removable Z-axis anisotropically conductive adhesive material (21) which includes water, a matrix resin (23), and conductive spheres (22). The material (21) is suitable for providing temporary contact between electronic devices. In one embodiment, the material (21) is used to temporarily bond a semiconductor wafer (11) to a probe substrate (12) for wafer-level burn-in.
摘要翻译：一种使用可移除的Z轴各向异性导电粘合剂材料（21）的方法，其包括水，基质树脂（23）和导电球体（22）。材料（21）适用于在电子设备之间提供临时接触。在一个实施例中，材料（21）用于将半导体晶片（11）临时粘合到用于晶片级老化的探针衬底（12）。

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