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    • 4. 发明授权
    • Low input resistance amplifier stage
    • 低输入电阻放大级
    • US5352989A
    • 1994-10-04
    • US62810
    • 1993-05-11
    • Christofer ToumazouMartin Anding
    • Christofer ToumazouMartin Anding
    • H03F3/30
    • H03F3/3001H03F3/3069
    • An amplifier stage suitable for current conveyors and current mode feedback operational amplifiers has low input resistance and operates at low power. The amplifier stage comprises a buffer having inverting and non-inverting inputs and a pair of current outputs, and a pair of multiple output current mirrors which operate in conjunction with the buffer to generate an output current at a high gain node in response to an input signal applied to the buffer inputs. Each multiple output current mirror has a low impedance current input for receiving current signals generated by the buffer and multiple high impedance current outputs for providing current feedback to the inverting input of the buffer and output current to the high gain node of the amplifier stage. The magnitudes of the feedback and output currents are determined by the resistances of current scaling resistors associated with the low impedance current input and each of the high impedance current outputs.
    • 适用于当前输送机和电流模式反馈运算放大器的放大器级具有低输入电阻并且以低功率运行。 放大器级包括具有反相和非反相输入和一对电流输出的缓冲器,以及一对多个输出电流镜,其与缓冲器一起工作,以响应于输入在高增益节点处产生输出电流 信号施加到缓冲器输入。 每个多输出电流反射镜具有低阻抗电流输入,用于接收由缓冲器产生的电流信号和多个高阻抗电流输出,用于向缓冲器的反相输入端提供电流反馈,并将输出电流输出到放大器级的高增益节点。 反馈和输出电流的大小由与低阻抗电流输入和每个高阻抗电流输出相关联的电流缩放电阻的电阻决定。
    • 8. 发明申请
    • CURRENT MODE LOGIC DIGITAL CIRCUITS
    • 电流模式逻辑数字电路
    • US20090219054A1
    • 2009-09-03
    • US12091727
    • 2006-10-27
    • Christofer ToumazouFrancesco Cannillo
    • Christofer ToumazouFrancesco Cannillo
    • H03K19/094
    • H03K19/09432H03K19/00384
    • A digital circuit comprises: a first arm including a first metal oxide semiconductor field effect transistor (M3) configured to act as a load device; a second arm including a second metal oxide semiconductor field effect transistor (M4) configured to act as a load device; and a switch (M1, M2) for selecting one of the first and second arms. Each of the first and second transistors (M3, M4) has a channel length of 100 nm or below and is biased to operate in the weak inversion regime. In an alternative circuit, each load device (M3, M4) has its bulk connected to its drain and is biased to operate in the weak inversion regime.
    • 数字电路包括:第一臂,包括被配置为用作负载装置的第一金属氧化物半导体场效应晶体管(M3); 第二臂,包括被配置为用作负载装置的第二金属氧化物半导体场效应晶体管(M4); 以及用于选择第一和第二臂之一的开关(M1,M2)。 第一和第二晶体管(M3,M4)中的每一个具有100nm或更小的沟道长度,并被偏置以在弱反转状态下操作。 在替代电路中,每个负载装置(M3,M4)的体积连接到其漏极并被偏置以在弱反转状态下工作。
    • 9. 发明授权
    • Hybrid digital/analog processing circuit
    • 混合数字/模拟处理电路
    • US06954163B2
    • 2005-10-11
    • US10486210
    • 2002-08-16
    • Christofer ToumazouAlison Burdett
    • Christofer ToumazouAlison Burdett
    • G06J1/00H03M1/66
    • G06J1/00
    • A circuit comprising a digital processor, analogue processing means, a digital to analogue converter for converting digital values output from the digital processor into analogue values which are processed by the analogue processing means, and an analogue to digital converter for converting resulting analogue values into digital values for input to the digital processor, wherein the analogue processing means comprises one or more analogue processors, and the circuit is dynamically reconfigurable under the control of the digital processor, such that analogue values are processed according to a first function by the analogue processing means, and following reconfiguration, analogue values are processed according to a second function by the analogue processing means.
    • 一种包括数字处理器,模拟处理装置,用于将从数字处理器输出的数字值转换成由模拟处理装置处理的模拟值的数模转换器的电路,以及用于将所得到的模拟值转换为数字 用于输入到数字处理器的值,其中所述模拟处理装置包括一个或多个模拟处理器,并且所述电路在数字处理器的控制下动态地可重新配置,使得模拟值根据模拟处理装置根据第一功能被处理 ,并且在重新配置之后,通过模拟处理装置根据第二功能处理模拟值。