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1. 发明授权

US06961827B2 Victim invalidation 有权
标题翻译：受害者无效
公开(公告)号：US06961827B2
公开(公告)日：2005-11-01
申请号：US10011115
申请日：2001-11-13
申请人： Patricia Shanahan , Andrew E. Phelps , Nicholas E. Aneshansley
发明人： Patricia Shanahan , Andrew E. Phelps , Nicholas E. Aneshansley
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/082 , G06F12/0808 , G06F12/0826 , G06F12/12
摘要： The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.
摘要翻译：本发明提供一种使受害条目无效的方法和装置。该装置包括适于存储一个或多个高速缓存条目的目录缓存器和控制单元。控制单元适于确定是否期望从目录高速缓存中移除共享高速缓存条目，并且响应于确定希望从目录高速缓存中移除共享高速缓存条目而使共享高速缓存条目无效。

2. 发明授权

US08028130B1 Pipeline structure for a shared memory protocol 有权
标题翻译：共享内存协议的管道结构
公开(公告)号：US08028130B1
公开(公告)日：2011-09-27
申请号：US10895812
申请日：2004-07-21
申请人： Steven F. Weiss , Andrew E. Phelps , Patricia Shanahan
发明人： Steven F. Weiss , Andrew E. Phelps , Patricia Shanahan
IPC分类号： G06F13/00 , G06F13/28 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F13/1657 , G06F15/16
摘要： A method and apparatus for implementation of a pipeline structure for data transfer. A request is received from a first domain to access a second domain during a first clock cycle. A pipeline structure is used to perform at least a portion of the request during a subsequent clock cycle.
摘要翻译：一种实现数据传输流水线结构的方法和装置。在第一时钟周期期间从第一域接收到访问第二域的请求。流水线结构用于在随后的时钟周期期间执行请求的至少一部分。

3. 发明授权

US07020753B2 Inter-domain data transfer 有权
公开(公告)号：US07020753B2
公开(公告)日：2006-03-28
申请号：US10042960
申请日：2002-01-09
申请人： Patricia Shanahan , Andrew E. Phelps , Guy David Frick
发明人： Patricia Shanahan , Andrew E. Phelps , Guy David Frick
IPC分类号： G06F12/00
CPC分类号： G06F12/0284 , G06F12/1081
摘要： The present invention provides a method and apparatus for inter-domain data transfer. The method includes mapping a memory region of a source device into a central device and mapping a memory region of a target device into the central device. The method further includes transferring data from the mapped memory region of the source device to the mapped memory region of the target device.

4. 发明授权

US06721852B2 Computer system employing multiple board sets and coherence schemes 有权
标题翻译：计算机系统采用多板集和一致性方案
公开(公告)号：US06721852B2
公开(公告)日：2004-04-13
申请号：US09981532
申请日：2001-10-17
申请人： Patricia Shanahan , Andrew E. Phelps
发明人： Patricia Shanahan , Andrew E. Phelps
IPC分类号： G06F1200
CPC分类号： G06F12/082
摘要： The present invention provides a method and apparatus for updating a directory cache. The method comprises detecting a memory access transaction, determining a retention value based on the type of memory access transaction, and storing the retention value in an entry associated with the memory access transaction.
摘要翻译：本发明提供了一种用于更新目录高速缓存的方法和装置。该方法包括检测存储器访问事务，基于存储器访问事务的类型确定保留值，以及将保留值存储在与存储器访问事务相关联的条目中。

5. 发明授权

US06571360B1 Cage for dynamic attach testing of I/O boards 有权
标题翻译：网卡用于I / O板的动态连接测试
公开(公告)号：US06571360B1
公开(公告)日：2003-05-27
申请号：US09422204
申请日：1999-10-19
申请人： Daniel P. Drogichen , Eric Eugene Graf , Don Kane , Douglas B. Meyer , Andrew E. Phelps , Patricia Shanahan , Steven F. Weiss
发明人： Daniel P. Drogichen , Eric Eugene Graf , Don Kane , Douglas B. Meyer , Andrew E. Phelps , Patricia Shanahan , Steven F. Weiss
IPC分类号： G06F1100
CPC分类号： G06F11/2733
摘要： A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested. The error cage isolates correction code errors, parity errors, protocol errors, timeout errors, and other similar errors generated by the I/O board under test. The address transaction cage isolates out of range memory addresses from the I/O board under test. The interrupt transaction cage isolates interrupt requests to an incorrect target port generated by the I/O board under test. The errors generated by the I/O board are logged in a status register and suppressed.
摘要翻译：多处理计算机系统提供硬件支持，以正确测试I / O板，同时系统正在运行用户应用程序，同时防止故障板导致系统崩溃。该系统包括一个安装多个扩展板的中心平面。每个扩展板又将微处理器板和I / O板连接到中心面。在进行测试之前，替换I / O板在插入多处理计算机系统的扩展板之后，将成为动态系统域软件分区的一部分。测试I / O板涉及在微处理器板上执行一个使用微处理器和存储器的过程来对I / O板进行硬件测试。错误笼，地址事务笼和中断事务笼隔离在测试I / O板时产生的任何错误。错误笼隔离了被测I / O板产生的校正码错误，奇偶校验错误，协议错误，超时错误以及其他类似的错误。地址事务笼隔离来自被测I / O板的范围内的存储器地址。中断事务笼将中断请求隔离到被测I / O板产生的目标端口不正确。 I / O板产生的错误记录在状态寄存器中并被抑制。

6. 发明授权

US5890131A Project organization and optimization tool and method of use thereof 失效
标题翻译：项目组织和优化工具及其使用方法
公开(公告)号：US5890131A
公开(公告)日：1999-03-30
申请号：US634961
申请日：1996-04-19
申请人： Justin C. Ebert , Scott H. Collins , John P. Arnold , Stephen L. David , Susan D. Dwyer , Michael D. Mills , Patricia Shanahan
发明人： Justin C. Ebert , Scott H. Collins , John P. Arnold , Stephen L. David , Susan D. Dwyer , Michael D. Mills , Patricia Shanahan
IPC分类号： G06Q10/04 , G06Q10/06 , G06Q10/10 , G06F17/60
CPC分类号： G06Q10/04 , G06Q10/063114 , G06Q10/063118 , G06Q10/1095
摘要： The present invention provides a project optimization software tool in which a single window in a graphical user interface serves as a tool for planning future actions, reviewing past actions, organizing meetings and launching executable software tools. A project pathway window supports: 1) the listing and viewing of sequences of pathway steps, which, if accomplished, lead towards a defined project goal, 2) the ability to link software tools to those pathway steps, and launch the software tools for execution, 3) the creation of meeting agendas, each of which may encompass several pathway steps, without demoting the included pathway steps, and 4) the marking of the status of pathway steps.
摘要翻译：本发明提供了一种项目优化软件工具，其中图形用户界面中的单个窗口用作用于规划未来动作，查看过去操作，组织会议和启动可执行软件工具的工具。项目路径窗口支持：1）路径步骤序列的列表和查看，如果完成，则导致定义的项目目标，2）将软件工具链接到这些路径步骤的能力，并启动执行的软件工具，3）创建会议议程，每个会议议程可能包含几个路径步骤，不排除所包含的路径步骤，以及4）路径步骤状态的标记。

7. 发明授权

US4761733A Direct-execution microprogrammable microprocessor system 失效
标题翻译：直接执行微程序微处理器系统
公开(公告)号：US4761733A
公开(公告)日：1988-08-02
申请号：US710615
申请日：1985-03-11
申请人： Andrew J. McCrocklin , Nicholas E. Aneshansley , Patricia Shanahan , James J. Whelan , Jeffrey P. Anderson , James E. Kocol , Gary L. Riddle
发明人： Andrew J. McCrocklin , Nicholas E. Aneshansley , Patricia Shanahan , James J. Whelan , Jeffrey P. Anderson , James E. Kocol , Gary L. Riddle
IPC分类号： G06F9/22 , G06F12/08 , G06F12/10
CPC分类号： G06F12/1063 , G06F12/0875 , G06F9/22
摘要： A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction address extension unit serving to communicate microinstructions from the main memory to the microprogrammable microprocessor. Virtual main memory accesses occur through a system multiplexer. A virtual address extension unit and a virtual address bus provide extension and redefinition of the main memory address space of the microprogrammable microprocessor. The system also uses a context switching stack cache and an expanded address translation cache with the microprogrammable microprocessor having a reduced and redefined microinstruction set with a variable microinstruction cycle.
摘要翻译：直接执行微程序微处理器系统使用可编程微程序微处理器来通过微指令端口直接执行主存储器中的微指令。具有微指令地址扩展单元的微指令缓存，用于将从主存储器的微指令传送到微程序微处理器。虚拟主存储器访问通过系统多路复用器进行。虚拟地址扩展单元和虚拟地址总线提供微程序微处理器的主存储器地址空间的扩展和重新定义。该系统还使用上下文切换堆栈高速缓存和扩展的地址转换高速缓存，其中微程序微处理器具有具有可变微指令周期的简化和重新定义的微指令集。

8. 发明授权

US06578111B1 Cache memory system and method for managing streaming-data 有权
标题翻译：缓存内存系统和管理流数据的方法
公开(公告)号：US06578111B1
公开(公告)日：2003-06-10
申请号：US09677093
申请日：2000-09-29
申请人： Peter C. Damron , Patricia Shanahan , Aleksandr Guzovskiy
发明人： Peter C. Damron , Patricia Shanahan , Aleksandr Guzovskiy
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0862 , G06F2212/6028
摘要： A system and method are provided for efficient handling of streaming-data in a cache memory system (105) having a cache with several cache-lines (160) capable of storing data. In one aspect, a method is provided for determining before storing data to a cache-line if the storing of data will replace earlier data already stored in cache (135). If the storing of data will replace data in the cache (135), it is determined if the data that will be replaced is streaming-data. If the data to be replaced is not streaming-data, it is stored into victim cache (155). However, if the data to be replaced is streaming-data, it is not stored into the victim cache, thereby improving system efficiency by eliminating the copying of data to be replaced and avoiding replacing other earlier data in victim cache (155) that may be needed in the future.
摘要翻译：提供了一种系统和方法，用于在具有能够存储数据的多个高速缓存行（160）的高速缓存的高速缓冲存储器系统（105）中有效地处理流数据。在一个方面，提供一种用于在将数据存储在高速缓存（135）中之前已经存储的数据的情况下将数据存储到高速缓存行之前进行确定的方法。如果数据的存储将替代高速缓存（135）中的数据，则确定将被替换的数据是否是流数据。如果要替换的数据不是流数据，则将其存储到受害缓存（155）中。然而，如果要替换的数据是流数据，则不将其存储到受害者缓存中，从而通过消除要被替换的数据的复制来提高系统效率，并且避免替换可能存在的受害缓存（155）中的其他较早数据将来需要。

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