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1. 发明授权

US06829700B2 Circuit and method for supporting misaligned accesses in the presence of speculative load instructions 有权
标题翻译：在存在投机负载指令的情况下支持不对准访问的电路和方法
公开(公告)号：US06829700B2
公开(公告)日：2004-12-07
申请号：US09751327
申请日：2000-12-29
申请人： Paolo Faraboschi , Alexander J. Starr , Geoffrey M. Brown , Mark Owen Homewood
发明人： Paolo Faraboschi , Alexander J. Starr , Geoffrey M. Brown , Mark Owen Homewood
IPC分类号： G06F9312
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/3816 , G06F9/383 , G06F9/3842 , G06F9/3861
摘要： There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.
摘要翻译：公开了一种数据处理器，包括：1）包括执行加载指令的N个处理级的指令执行流水线; 2）用于存储可修改配置值的状态寄存器，具有指示数据处理器的第一值的可修改配置值能够执行未对准访问处理例程，并且指示数据处理器的第二值不能执行未对准访问处理常规; 3）一种用于确定所述加载指令是否对所述加载指令的目标地址进行不对准访问的错位检测电路，并且响应于所述加载指令确实执行未对准访问的确定，产生未对准标志; 以及4）异常控制电路，其能够检测所述未对准标志，并且响应于此确定所述可修改配置值是否等于所述第一值。

2. 发明授权

US06922773B2 System and method for encoding constant operands in a wide issue processor 有权
标题翻译：用于在广泛问题处理器中对常量操作数进行编码的系统和方法
公开(公告)号：US06922773B2
公开(公告)日：2005-07-26
申请号：US09751408
申请日：2000-12-29
申请人： Paolo Faraboschi , Alexander J. Starr , Anthony X. Jarvis , Geoffrey M. Brown , Mark Owen Homewood , Gary L. Vondran
发明人： Paolo Faraboschi , Alexander J. Starr , Anthony X. Jarvis , Geoffrey M. Brown , Mark Owen Homewood , Gary L. Vondran
IPC分类号： G06F9/30 , G06F9/38 , G06F9/34
CPC分类号： G06F9/3891 , G06F9/3016 , G06F9/30167 , G06F9/30178 , G06F9/3853 , G06F9/3885
摘要： For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.
摘要翻译：为了在包括N个处理级的指令执行流水线的数据处理器中使用，公开了对常数操作数进行编码的系统和方法。该系统包括能够产生短常数操作数和长常数操作数的恒定发电机单元。常数发生器单元从指令音节中提取短常量操作数的位，右对齐输出音节中的位。对于长常数操作数，常数发生器单元从扩展音节从指令音节和T高位比特提取K个低位比特。右对齐K低位位和T高位位组合以表示一个输出音节中的长常数操作数。响应于位于恒定生成指令内的操作码位的状态，常数发生器单元启用和禁用多路复用器自动生成适当的短或长常数操作数。

3. 发明授权

US07779240B2 System and method for reducing power consumption in a data processor having a clustered architecture 有权
标题翻译：具有集群架构的数据处理器中的功耗降低的系统和方法
公开(公告)号：US07779240B2
公开(公告)日：2010-08-17
申请号：US11900978
申请日：2007-09-14
申请人： Mark Owen Homewood , Gary L. Vondran , Geoffrey M. Brown , Paolo Faraboschi
发明人： Mark Owen Homewood , Gary L. Vondran , Geoffrey M. Brown , Paolo Faraboschi
IPC分类号： G06F9/00
CPC分类号： G06F9/30058 , G06F9/3885
摘要： There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.
摘要翻译：公开了一种数据处理器，其具有包括至少一个分支簇，至少一个非分支簇和远程条件分支控制电路的集群架构。每个集群都能够计算分支条件，尽管只有分支集群可用于执行分支地址计算。响应于感测非分支集群中的条件分支指令，可以操作与每个集群相关联的远程条件分支控制电路，以（i）使分支集群计算分支地址和下一个程序计数器（ii）使非分支集群计算分支条件，并且（iii）将所计算的分支条件从非分支集群传递到分支集群。然后，数据处理器使用计算出的分支条件来选择分支地址或下一个程序计数器地址之一。

4. 发明授权

US07337306B2 Executing conditional branch instructions in a data processor having a clustered architecture 有权
标题翻译：在具有集群架构的数据处理器中执行条件转移指令
公开(公告)号：US07337306B2
公开(公告)日：2008-02-26
申请号：US09751410
申请日：2000-12-29
申请人： Mark Owen Homewood , Gary L. Vondran , Geoffrey M. Brown , Paolo Faraboschi
发明人： Mark Owen Homewood , Gary L. Vondran , Geoffrey M. Brown , Paolo Faraboschi
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/3885
摘要： There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.
摘要翻译：公开了一种数据处理器，其具有包括至少一个分支簇，至少一个非分支簇和远程条件分支控制电路的集群架构。每个集群都能够计算分支条件，尽管只有分支集群可用于执行分支地址计算。响应于感测非分支集群中的条件分支指令，可以操作与每个集群相关联的远程条件分支控制电路，以（i）使分支集群计算分支地址和下一个程序计数器（ii）使非分支集群计算分支条件，并且（iii）将所计算的分支条件从非分支集群传递到分支集群。然后，数据处理器使用计算出的分支条件来选择一个分支地址或下一个程序计数器地址。

5. 发明授权

US07143268B2 Circuit and method for instruction compression and dispersal in wide-issue processors 有权
标题翻译：广泛处理器中指令压缩和扩散的电路和方法
公开(公告)号：US07143268B2
公开(公告)日：2006-11-28
申请号：US09751674
申请日：2000-12-29
申请人： Paolo Faraboschi , Anthony X. Jarvis , Mark Owen Homewood , Geoffrey M. Brown , Gary L. Vondran
发明人： Paolo Faraboschi , Anthony X. Jarvis , Mark Owen Homewood , Geoffrey M. Brown , Gary L. Vondran
IPC分类号： G06F9/30
CPC分类号： G06F9/3891 , G06F9/30054 , G06F9/30101 , G06F9/3802 , G06F9/3853 , G06F9/3885
摘要： A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline is a number of lanes wide. The processing stages execute instruction bundles, where each instruction bundle has one or more syllables. Each lane is capable of receiving one of the syllables of an instruction bundle. The instruction cache includes a number of cache lines. The instruction issue unit receives fetched cache lines and issues complete instruction bundles toward the execution clusters. The alignment and dispersal circuitry receives the complete instruction bundles from the instruction issue unit and routes each received complete instruction bundle to a correct one of the execution clusters. The complete instruction bundles are routed as a function of at least one address bit associated with each complete instruction bundle.
摘要翻译：数据处理器包括执行集群，指令高速缓存，指令发布单元以及对准和分散电路。每个执行集群包括具有多个处理阶段的指令执行流水线，并且每个执行流水线都是多个通道。处理阶段执行指令束，其中每个指令束具有一个或多个音节。每个通道能够接收指令束的一个音节。指令高速缓存包含多条缓存行。指令发布单元接收获取的高速缓存行并向执行群发出完整的指令束。对齐和分散电路从指令发布单元接收完整的指令束，并将每个接收的完整指令包路由到正确的一个执行簇。完整的指令束作为与每个完整指令束相关联的至少一个地址位的功能进行路由。

6. 发明授权

US06807628B2 System and method for supporting precise exceptions in a data processor having a clustered architecture 有权
标题翻译：用于在具有集群架构的数据处理器中支持精确异常的系统和方法
公开(公告)号：US06807628B2
公开(公告)日：2004-10-19
申请号：US09751330
申请日：2000-12-29
申请人： Mark Owen Homewood , Anthony X. Jarvis , Alexander J. Starr
发明人： Mark Owen Homewood , Anthony X. Jarvis , Alexander J. Starr
IPC分类号： G06F938
CPC分类号： G06F9/3891 , G06F9/3865 , G06F9/3885
摘要： There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters and an interrupt and exception controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The interrupt and exception controller operates to (i) detect an exception condition associated with one of the executing instructions, wherein this executing instruction issued at time t0, and (ii) generate an exception in response to the exception condition upon completed execution of earlier ones of the executing instructions, these earlier executing instructions issued at time preceding t0.
摘要翻译：公开了一种数据处理器，其具有包括多个集群和中断和异常控制器的集群架构。每个簇包括具有N个处理阶段的指令执行流水线。 N个处理阶段中的每一个能够执行与由集群执行的指令相关联的多个执行步骤中的至少一个。中断和异常控制器操作以（i）检测与执行指令之一相关联的异常条件，其中在时间t0发出的执行指令，和（ii）在完成执行之后根据异常条件产生异常执行指令的这些早期执行指令在t0之前发出。

7. 发明申请

US20140146814A1 SWITCH DEVICE 有权
标题翻译：开关装置
公开(公告)号：US20140146814A1
公开(公告)日：2014-05-29
申请号：US13820094
申请日：2011-08-31
申请人： Anthony Michael Ford , James Tilbrook Corke , Neil Alexander Shute , Mark Owen Homewood
发明人： Anthony Michael Ford , James Tilbrook Corke , Neil Alexander Shute , Mark Owen Homewood
IPC分类号： H04L12/933
CPC分类号： H04L49/10 , H04Q1/145
摘要： A switch device for use in telecommunications apparatus, the switch device comprising: a substantially planar substrate having first substantially planar face and an opposing second substantially planar face; a first plurality of ports mounted on the first face of the substrate, and having a first arrangement of locating pins which extend into the substrate from the first face towards the second face thereof; and a second plurality of ports mounted on the second face of the substrate, and having a second arrangement of locating pins which extend into the substrate from the second face towards the first face thereof, wherein the first arrangement of locating pins is offset with respect to the second arrangement of locating pins.
摘要翻译：一种用于电信设备的开关装置，所述开关装置包括：基本上平面的基板，具有第一基本平坦的面和相对的第二基本平坦的面; 第一多个端口，安装在基板的第一面上，并且具有定位从第一面朝向第二面延伸到基板中的销的第一布置; 以及安装在所述基板的第二面上的第二多个端口，并且具有定位从所述第二面向其第一面延伸到所述基板中的销的第二布置，其中所述定位销的所述第一布置相对于定位销的第二种布置。

8. 发明授权

US09413690B2 Switch device 有权
标题翻译：开关装置
公开(公告)号：US09413690B2
公开(公告)日：2016-08-09
申请号：US13820094
申请日：2011-08-31
申请人： Anthony Michael Ford , James Tilbrook Corke , Neil Alexander Shute , Mark Owen Homewood
发明人： Anthony Michael Ford , James Tilbrook Corke , Neil Alexander Shute , Mark Owen Homewood
IPC分类号： H05K7/00 , H04L12/933 , H04Q1/14
CPC分类号： H04L49/10 , H04Q1/145
摘要： A switch device for use in telecommunications apparatus, the switch device comprising: a substantially planar substrate having first substantially planar face and an opposing second substantially planar face; a first plurality of ports mounted on the first face of the substrate, and having a first arrangement of locating pins which extend into the substrate from the first face towards the second face thereof; and a second plurality of ports mounted on the second face of the substrate, and having a second arrangement of locating pins which extend into the substrate from the second face towards the first face thereof, wherein the first arrangement of locating pins is offset with respect to the second arrangement of locating pins.
摘要翻译：一种用于电信设备的开关装置，所述开关装置包括：基本上平面的基板，具有第一基本平坦的面和相对的第二基本平坦的面; 第一多个端口，安装在基板的第一面上，并且具有定位从第一面朝向第二面延伸到基板中的销的第一布置; 以及安装在所述基板的第二面上的第二多个端口，并且具有定位从所述第二面向其第一面延伸到所述基板中的销的第二布置，其中所述定位销的所述第一布置相对于定位销的第二种布置。

9. 发明授权

US09401876B2 Method of data delivery across a network fabric in a router or Ethernet bridge 有权
标题翻译：通过路由器或以太网桥中的网络结构进行数据传输的方法
公开(公告)号：US09401876B2
公开(公告)日：2016-07-26
申请号：US12990370
申请日：2009-04-29
申请人： Jon Beecroft , David Charles Hewson , Anthony Michael Ford , Mark Owen Homewood
发明人： Jon Beecroft , David Charles Hewson , Anthony Michael Ford , Mark Owen Homewood
IPC分类号： H04L12/701 , H04L12/935 , H04L12/931
CPC分类号： H04L12/4633 , H04L49/3009 , H04L49/351 , H04L2212/00
摘要： The invention provides an Ethernet bridge or router comprising a network fabric adapted to provide interconnectivity to a plurality of Ethernet ports, each of the Ethernet ports being adapted to receive and/or transmit Ethernet frames, and wherein the Ethernet bridge or router further comprises an encapsulator connected to receive Ethernet Protocol Data Units from the Ethernet ports, wherein the encapsulator is operable to generate a Fabric Protocol Data Unit from a received Ethernet Protocol Data Unit, the Fabric Protocol Data Unit comprising a header portion, and a payload portion which comprises the Ethernet Protocol Data Unit concerned, and wherein the encapsulator is operable to transform Ethernet destination address information from the Ethernet Protocol Data Unit into a routing definition for the network fabric, and to include this routing definition in the header portion of the Fabric Protocol Data Unit. Also provided is a method of data delivery across a network.
摘要翻译：本发明提供了一种以太网桥或路由器，其包括适于提供与多个以太网端口的互连性的网络结构，每个以太网端口适于接收和/或发送以太网帧，并且其中所述以太网桥或路由器还包括封装器连接以从以太网端口接收以太网协议数据单元，其中所述封装器可操作以从接收到的以太网协议数据单元生成结构协议数据单元，所述结构协议数据单元包括报头部分和包括以太网的有效载荷部分协议数据单元，并且其中所述封装器可操作以将以太网目的地地址信息从以太网协议数据单元转换为所述网络结构的路由定义，并将所述路由定义包括在所述结构协议数据单元的报头部分中。还提供了一种通过网络进行数据传送的方法。

10. 发明申请

US20110170553A1 METHOD OF DATA DELIVERY ACROSS A NETWORK FABRIC IN A ROUTER OR ETHERNET BRIDGE 有权
标题翻译：在路由器或以太网桥中的网络布线的数据传送方法
公开(公告)号：US20110170553A1
公开(公告)日：2011-07-14
申请号：US12990370
申请日：2009-04-29
申请人： Jon Beecroft , David Charles Hewson , Anthony Michael Ford , Mark Owen Homewood
发明人： Jon Beecroft , David Charles Hewson , Anthony Michael Ford , Mark Owen Homewood
IPC分类号： H04L12/56
CPC分类号： H04L12/4633 , H04L49/3009 , H04L49/351 , H04L2212/00
摘要： The invention provides an Ethernet bridge or router comprising a network fabric adapted to provide interconnectivity to a plurality of Ethernet ports, each of the Ethernet ports being adapted to receive and/or transmit Ethernet frames, and wherein the Ethernet bridge or router further comprises an encapsulator connected to receive Ethernet Protocol Data Units from the Ethernet ports, wherein the encapsulator is operable to generate a Fabric Protocol Data Unit from a received Ethernet Protocol Data Unit, the Fabric Protocol Data Unit comprising a header portion, and a payload portion which comprises the Ethernet Protocol Data Unit concerned, and wherein the encapsulator is operable to transform Ethernet destination address information from the Ethernet Protocol Data Unit into a routing definition for the network fabric, and to include this routing definition in the header portion of the Fabric Protocol Data Unit. Also provided is a method of data delivery across a network.
摘要翻译：本发明提供了一种以太网桥或路由器，其包括适于提供与多个以太网端口的互连性的网络结构，每个以太网端口适于接收和/或发送以太网帧，并且其中所述以太网桥或路由器还包括封装器连接以从以太网端口接收以太网协议数据单元，其中所述封装器可操作以从接收到的以太网协议数据单元生成结构协议数据单元，所述结构协议数据单元包括报头部分和包括以太网的有效载荷部分协议数据单元，并且其中所述封装器可操作以将以太网目的地地址信息从以太网协议数据单元转换为所述网络结构的路由定义，并将所述路由定义包括在所述结构协议数据单元的报头部分中。还提供了一种通过网络进行数据传送的方法。

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