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1. 发明授权

US06331237B1 Method of improving contact reliability for electroplating 失效
标题翻译：提高电镀接触可靠性的方法
公开(公告)号：US06331237B1
公开(公告)日：2001-12-18
申请号：US09387856
申请日：1999-09-01
申请人： Panayotis C. Andricacos , W. Jean Horkans , Keith T. Kwietniak , Peter S. Locke , Cyprian E. Uzoh
发明人： Panayotis C. Andricacos , W. Jean Horkans , Keith T. Kwietniak , Peter S. Locke , Cyprian E. Uzoh
IPC分类号： C25D2106
CPC分类号： C25D7/123 , C25D5/003 , C25D21/12 , C25D21/18
摘要： A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.
摘要翻译：通过电镀液减少种子层的蚀刻的方法。在将具有种子层的半导体晶片引入电镀液之前，电镀液的蚀刻功率降低。

2. 发明授权

US06344129B1 Method for plating copper conductors and devices formed 有权
标题翻译：电镀铜导体和器件的方法
公开(公告)号：US06344129B1
公开(公告)日：2002-02-05
申请号：US09418197
申请日：1999-10-13
申请人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
发明人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
IPC分类号： C25D500
CPC分类号： C25D5/10 , C25D3/38 , C25D5/00 , C25D7/123 , C25D21/02 , H05K3/423
摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.
摘要翻译：公开了一种在电子基板上镀铜导体的方法和形成的器件。在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如双镶嵌结构中的通孔，其直径/深度的纵横比大于1/3或高达{分数（ 1/10）}。各种电镀参数用于在单步沉积或双步沉积工艺中提供短电阻瞬变。这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

3. 发明授权

US06979393B2 Method for plating copper conductors and devices formed 失效
标题翻译：电镀铜导体和器件的方法
公开(公告)号：US06979393B2
公开(公告)日：2005-12-27
申请号：US10055134
申请日：2002-01-22
申请人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
发明人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
IPC分类号： C25D3/38 , C25D5/00 , C25D5/10 , C25D7/12 , H05K3/42 , C25D5/02
CPC分类号： C25D5/10 , C25D3/38 , C25D5/00 , C25D7/123 , C25D21/02 , H05K3/423
摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.
摘要翻译：公开了一种在电子基板上镀铜导体的方法和形成的器件。在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如具有大于1/3或高达1的直径/深度的纵横比的双镶嵌结构中的通孔 / 10。各种电镀参数用于在单步沉积或双步沉积过程中提供短电阻瞬变。这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

4. 发明授权

US07227265B2 Electroplated copper interconnection structure, process for making and electroplating bath 有权
标题翻译：电镀铜互连结构，制作工艺和电镀浴
公开(公告)号：US07227265B2
公开(公告)日：2007-06-05
申请号：US10810719
申请日：2004-03-29
申请人： Panayotis C. Andricacos , Steven H. Boettcher , Dean S. Chung , Hariklia Deligianni , James E. Fluegel , Wilma Jean Horkans , Keith T. Kwietniak , Peter S. Locke , Christopher C. Parks , Soon-Cheon Seo , Andrew H. Simon , Erick G. Walton
发明人： Panayotis C. Andricacos , Steven H. Boettcher , Dean S. Chung , Hariklia Deligianni , James E. Fluegel , Wilma Jean Horkans , Keith T. Kwietniak , Peter S. Locke , Christopher C. Parks , Soon-Cheon Seo , Andrew H. Simon , Erick G. Walton
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/2885 , C25D3/38 , C25D5/024 , C25D5/18 , C25D7/123 , H01L21/76877
摘要： Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 μm and via openings filled with electroplated copper than is substantially free of internal seams or voids.
摘要翻译：使用包含溶解的铜盐的电镀铜浴获得至少基本上不含内部接缝或空隙的铜导体的互连结构，其中盐的浓度为酸的至少约0.4摩尔浓度至高达约0.5摩尔浓度。还提供了具有大于约3的宽高比和小于约0.275μm的宽度的铜镶嵌结构以及填充有电镀铜的通孔，基本上不含内部接缝或空隙。

5. 发明授权

US06251251B1 Anode design for semiconductor deposition 失效
标题翻译：用于半导体沉积的阳极设计
公开(公告)号：US06251251B1
公开(公告)日：2001-06-26
申请号：US09192431
申请日：1998-11-16
申请人： Cyprian E. Uzoh , Panayotis C. Andricacos , John Owen Dukovic , Robert P. Westerfield, Jr.
发明人： Cyprian E. Uzoh , Panayotis C. Andricacos , John Owen Dukovic , Robert P. Westerfield, Jr.
IPC分类号： C25D2118
CPC分类号： C25D7/12 , C25D17/001 , C25D17/12
摘要： An anode assembly including a perforated anode. A perforated anode holder holds the anode. The anode holder includes perforations at least in a bottom wall such that plating solution may flow through perforations in the anode holder and perforations in the anode. An anode isolator separates the anode and a cathode. The anode isolator includes at least one curvilinear surface.
摘要翻译：包括穿孔阳极的阳极组件。穿孔阳极支架固定阳极。阳极保持器至少在底壁中具有穿孔，使得电镀溶液可以流过阳极保持器中的穿孔和阳极中的穿孔。阳极隔离器分离阳极和阴极。阳极隔离器包括至少一个曲线表面。

6. 发明授权

US06471845B1 Method of controlling chemical bath composition in a manufacturing environment 有权
标题翻译：在制造环境中控制化学浴组成的方法
公开(公告)号：US06471845B1
公开(公告)日：2002-10-29
申请号：US09461849
申请日：1999-12-15
申请人： John O. Dukovic , William E. Corbin, Jr. , Erick G. Walton , Peter S. Locke , Panayotis C. Andricacos , James E. Fluegel , Evan Patton , Jonathan Reid
发明人： John O. Dukovic , William E. Corbin, Jr. , Erick G. Walton , Peter S. Locke , Panayotis C. Andricacos , James E. Fluegel , Evan Patton , Jonathan Reid
IPC分类号： C25D2112
CPC分类号： C25D21/12 , Y10T137/2509
摘要： A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.
摘要翻译：用于控制化学浴的组成的方法，其中使用预测剂量来解释浴的组成的变化，其中过程的操作特性被划分为多种操作模式以及相关材料的消耗或产生根据经验确定该过程，并酌情添加材料。

7. 发明申请

US20100051474A1 METHOD AND COMPOSITION FOR ELECTRO-CHEMICAL-MECHANICAL POLISHING 审中-公开
标题翻译：电化学机械抛光方法与组合
公开(公告)号：US20100051474A1
公开(公告)日：2010-03-04
申请号：US12548893
申请日：2009-08-27
申请人： Panayotis C. Andricacos , Caliopi Andricacos , Donald F. Canaperi , Emanuel I. Cooper , John M. Cotte , Hariklia Deligianni , Laertis Economikos , Daniel C. Edelstein , Silvia Franz , Balasubramanian Pranatharthiharan , Mahadevaiyer Krishnan , Andrew P. Mansson , Erick G. Walton , Alan C. West
发明人： Panayotis C. Andricacos , Caliopi Andricacos , Donald F. Canaperi , Emanuel I. Cooper , John M. Cotte , Hariklia Deligianni , Laertis Economikos , Daniel C. Edelstein , Silvia Franz , Balasubramanian Pranatharthiharan , Mahadevaiyer Krishnan , Andrew P. Mansson , Erick G. Walton , Alan C. West
IPC分类号： B23H5/06
CPC分类号： C25F3/02 , B23H5/08 , C09G1/04 , H01L21/32125
摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.
摘要翻译：提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

8. 发明授权

US07190079B2 Selective capping of copper wiring 失效
标题翻译：铜线选择性封盖
公开(公告)号：US07190079B2
公开(公告)日：2007-03-13
申请号：US11265302
申请日：2005-11-03
申请人： Panayotis C. Andricacos , Shyng-Tsong Chen , John M. Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe M. Vereecken
发明人： Panayotis C. Andricacos , Shyng-Tsong Chen , John M. Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe M. Vereecken
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/6708 , H01L21/76849 , H01L21/7685 , H01L21/76874 , H01L21/76883
摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
摘要翻译：通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

9. 发明授权

US07638406B2 Method of fabricating a high Q factor integrated circuit inductor 有权
标题翻译：制造高Q因子集成电路电感的方法
公开(公告)号：US07638406B2
公开(公告)日：2009-12-29
申请号：US11320375
申请日：2005-12-28
申请人： Daniel C. Edelstein , Panayotis C. Andricacos , John M. Cotte , Hariklia Deligianni , John H. Magerlein , Kevin S. Petrarca , Kenneth J. Stein , Richard P. Volant
发明人： Daniel C. Edelstein , Panayotis C. Andricacos , John M. Cotte , Hariklia Deligianni , John H. Magerlein , Kevin S. Petrarca , Kenneth J. Stein , Richard P. Volant
IPC分类号： H01L21/20
CPC分类号： H01L24/12 , H01L23/5227 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L27/08 , H01L28/10 , H01L2224/0401 , H01L2224/04042 , H01L2224/05007 , H01L2224/05014 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05084 , H01L2224/05555 , H01L2224/05557 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/48744 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19042 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.
摘要翻译：一种形成电感器的方法。该方法包括：在基板上形成电介质层; 在介电层中形成下沟槽; 在下沟槽和电介质层上形成衬垫; 在衬套上形成Cu籽晶层; 在Cu籽晶层上形成抗蚀剂层; 在抗蚀剂层中形成上沟槽; 电镀Cu以完全填充下沟槽并且至少部分地填充上沟槽; 去除抗蚀剂层; 在所有暴露的Cu表面上选择性地形成钝化层; 从所述衬垫的区域选择性地去除所述Cu籽晶层; 以及从所述电介质层去除所述衬垫的这样暴露的区域，其中所述电感器的顶表面延伸到所述电介质层的顶表面之上，所述钝化层保留在所述电介质的位于所述电介质层的顶表面之上的侧壁的区域上。

10. 发明授权

US06992389B2 Barrier for interconnect and method 失效
标题翻译：屏障互连和方法
公开(公告)号：US06992389B2
公开(公告)日：2006-01-31
申请号：US10709321
申请日：2004-04-28
申请人： Panayotis C. Andricacos , Tien-Jen J. Cheng , Emanuel I. Cooper , David E. Eichstadt , Jonathan H. Griffith , Randolph F. Knarr , Roger A. Quon , Erik J. Roggeman
发明人： Panayotis C. Andricacos , Tien-Jen J. Cheng , Emanuel I. Cooper , David E. Eichstadt , Jonathan H. Griffith , Randolph F. Knarr , Roger A. Quon , Erik J. Roggeman
IPC分类号： H01L23/48 , H01L23/52 , H01L21/60 , H01L23/485
CPC分类号： H01L21/2885 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05155 , H01L2224/05647 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04953 , H01L2924/01028 , H01L2924/00014
摘要： A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.
摘要翻译：创建用于在互连中使用的多层屏障的方法，用于互连的阻挡，以及包括该阻挡互连中公开。该方法包括通过使用单个电镀化学品在器件端子的凹部中产生多层屏障，以增强由于铜的扩散而导致的排除和去层压的保护，无论是通过自扩散还是电迁移。所述屏障至少包括富镍材料制成的第一层和富铜材料制成的第二层。该屏障允许使用用于高级互补金属氧化物半导体（CMOS）的设计更高的电流密度的，并延伸当前的CMOS的可靠性设计不管焊料选择。此外，这种技术很容易适应制造电镀互连，如C4S的当前方法。

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