专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2004010321A3 PROCESSOR ARRAY 审中-公开
标题翻译：处理器阵列
公开(公告)号：WO2004010321A3
公开(公告)日：2005-03-31
申请号：PCT/GB0302772
申请日：2003-06-27
申请人： PICOCHIP DESIGNS LTD , ROBBINS WILLIAM , DAVIDSON MICHAEL , HOWELL SIMON , CLAYDON ANTHONY PETER JOHN
发明人： ROBBINS WILLIAM , DAVIDSON MICHAEL , HOWELL SIMON , CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F15/80 , G06F11/20 , G11C29/00
CPC分类号： G06F11/2051 , G06F11/2038 , G06F11/2041
摘要： An array of processing elements can incorporate a degree of redundancy. Specifically, the array includes one or more spare, or redundant, rows of array elements, in addition to the number required to implement the intended function or functions of the device. If a defect occurs in one of the processors in the device, then the entire row which includes that defective processor is not used, and is replaced by a spare row.
摘要翻译：一系列处理元件可以并入一定程度的冗余。具体而言，除了实现设备的预期功能或功能所需的数量之外，该阵列还包括一个或多个备用或冗余的数组元素行。如果设备中的一个处理器中出现缺陷，则不使用包含该缺陷处理器的整个行，并由备用行替换。

2. 发明申请

WO2004074962A2 PROCESSOR NETWORK 审中-公开
标题翻译：处理器网络
公开(公告)号：WO2004074962A2
公开(公告)日：2004-09-02
申请号：PCT/GB2004000670
申请日：2004-02-19
申请人： PICOCHIP DESIGNS LTD , DULLER ANDREW , PANESAR GAJINDER , GRAY ALAN , CLAYDON ANTHONY PETER JOHN , ROBBINS WILLIAM PHILIP
发明人： DULLER ANDREW , PANESAR GAJINDER , GRAY ALAN , CLAYDON ANTHONY PETER JOHN , ROBBINS WILLIAM PHILIP
IPC分类号： G06F20060101 , G06F9/445 , G06F9/45 , G06F9/46 , G06F9/50 , G06F
CPC分类号： G06F9/5066 , G06F8/451
摘要： Processes are automatically allocated to processors in a processor array, and corresponding communications resources are assigned at compile time, using information provided by the programmer. The processing tasks in the array are therefore allocated in such a way that the resources required to communicate data between the different processors are guaranteed.
摘要翻译：过程被自动分配给处理器阵列中的处理器，并且使用编程器提供的信息在编译时分配对应的通信资源。因此，阵列中的处理任务被分配成使得在不同处理器之间传送数据所需的资源得到保证。

3. 发明申请

WO2004074963A3 COMMUNICATIONS IN A PROCESSOR ARRAY 审中-公开
标题翻译：处理器阵列中的通信
公开(公告)号：WO2004074963A3
公开(公告)日：2005-01-27
申请号：PCT/GB2004000673
申请日：2004-02-19
申请人： PICOCHIP DESIGNS LTD , PANESAR GAJINDER , CLAYDON ANTHONY PETER JOHN , ROBBINS WILLIAM PHILIP , ORR ALEX , DULLER ANDREW
发明人： PANESAR GAJINDER , CLAYDON ANTHONY PETER JOHN , ROBBINS WILLIAM PHILIP , ORR ALEX , DULLER ANDREW
IPC分类号： G06F13/14 , G06F20060101 , G06F13/38 , G06F13/42 , G06F15/173 , G06F15/80
CPC分类号： G06F13/4286
摘要： Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data. If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.
摘要翻译：在所分配的时隙期间，数据从发送处理器通过网络传送到一个或多个接收处理器，并且在相同的分配时隙期间以相反的方向发送确认信号，以指示接收处理器是否能够接收数据。如果一个或多个接收处理器指示它不能接收数据，则在下一个分配的时隙期间重传该数据。这意味着发送处理器能够在时隙周期内确定是否需要重传，但是时隙周期只需要足够长以进行单向通信。

4. 发明申请

WO0250700A3 PROCESSOR ARCHITECTURE 审中-公开
标题翻译：处理器架构
公开(公告)号：WO0250700A3
公开(公告)日：2003-11-06
申请号：PCT/GB0104685
申请日：2001-10-19
申请人： PICOCHIP DESIGNS LTD , CLAYDON ANTHONY PETER JOHN
发明人： CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F7/00 , G06F1/32 , G06F9/38 , G06F13/36 , G06F15/80 , G06F1/10
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3287 , G06F9/3824 , G06F9/3885 , G06F15/8007 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： There is described a processor architecture having a plurality of processing elements, each element having at least one input port and at least one output port, each port having at least a data bus and a valid data signal line; and a bus structure which contains a plurality of switches which are arranged so as to allow an output port of any first processing element to be connected to the input port of any second processing element for a time interval, in which each processing element is enabled to set a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value, and to a second logic state when the data bus does not contain a transfer value, and in which each processing element is further enabled to enter a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state. This reduces the power consumption of the device.
摘要翻译：描述了具有多个处理元件的处理器架构，每个元件具有至少一个输入端口和至少一个输出端口，每个端口至少具有数据总线和有效数据信号线; 以及总线结构，其包含多个开关，其布置成允许任何第一处理元件的输出端口连接到任何第二处理元件的输入端口一段时间间隔，其中每个处理元件被允许当相关联的数据总线包含转移值时，将其输出端口的有效数据信号线上的值设置为第一逻辑状态，并且当数据总线不包含转移值时将值设置为第二逻辑状态，并且其中每个处理当相关联的输入端口的有效数据信号线上的值处于第二逻辑状态时，元件还能够进入预定时间间隔的等待状态。这降低了设备的功耗。

5. 发明申请

WO0250624A3 PROCESSOR ARCHITECTURE 审中-公开
标题翻译：处理器架构
公开(公告)号：WO0250624A3
公开(公告)日：2003-10-16
申请号：PCT/GB0104665
申请日：2001-10-19
申请人： PICOCHIP DESIGNS LTD , CLAYDON ANTHONY PETER JOHN , CLAYDON ANNE PATRICIA
发明人： CLAYDON ANTHONY PETER JOHN , CLAYDON ANNE PATRICIA
IPC分类号： G06F7/00 , G06F15/80
CPC分类号： G06F15/8023
摘要： There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs,each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array.
摘要翻译：描述了一种处理器架构，包括：多个第一总线对，每个第一总线对包括在第一方向（例如从左到右）上运行的相应的第一总线，以及以与第二总线相对的第二方向运行的相应的第二总线第一个方向（例如从右到左）; 多个第二总线对，每个第二总线对包括沿第三方向（例如向下）行进的相应的第三总线和沿与第三方向（例如向上）相反的第四方向行进的相应的第四总线，第三总线和第四辆巴士与第一和第二辆公交车相交; 多个开关矩阵，每个开关矩阵位于第一和第二对总线的交点处; 以阵列布置的多个元件，每个元件被布置成从相应的第一或第二总线接收数据，并将数据传送到相应的第一或第二总线。阵列中的元件包括用于对接收到的数据进行操作的处理元件和用于存储接收数据的存储器元件。所描述的架构的优点在于它需要相对较少的存储器，并且存储器要求可以由阵列中的本地存储器元件来满足。

6. 发明专利

JP2008226275A Processor architecture 审中-公开
标题翻译：处理器架构
公开(公告)号：JP2008226275A
公开(公告)日：2008-09-25
申请号：JP2008149976
申请日：2008-06-06
申请人： Picochip Designs Ltd , ピコチップデザインズリミテッド
发明人： CLAYDON ANTHONY PETER JOHN , CLAYDON ANNE PATRICIA
IPC分类号： G06F7/00 , G06F13/36 , G06F15/173 , G06F15/80
CPC分类号： G06F15/8023
摘要： PROBLEM TO BE SOLVED: To operate a large number of various algorithms requested simultaneously by a radio communication software, without reconstructing an array in a device, by permitting a flexible data output between array elements, using a switch matrix, in an architecture. SOLUTION: This processor architecture has a plurality of bus pairs including the first bus traveling along the first direction and the second bus traveling along the second direction opposite to the first direction, the plurality of elements connected between the bus, that is any of the plurality of bus pairs, and the second bus, and the plurality of switch matrixes connected to the plurality of bus pairs, and each of the plurality of switch matrixes connects selectively the first bus of the first bus pair out of double adjacent ones, to the second bus of the second bus pair adjacent to the first bus pair. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了操作由无线电通信软件同时请求的大量各种算法，而不需要重新构建设备中的阵列，通过允许在架构中使用开关矩阵的阵列元件之间的灵活数据输出。解决方案：该处理器架构具有多个总线对，包括沿着第一方向行进的第一总线和沿着与第一方向相反的第二方向行进的第二总线，多个元件连接在总线之间，即任何多个总线对和第二总线以及连接到多个总线对的多个开关矩阵，并且多个开关矩阵中的每一个开关矩阵选择性地连接双相邻的第一总线对的第一总线，到与第一总线对相邻的第二总线对的第二总线。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2009054154A Processor architecture 审中-公开
标题翻译：处理器架构
公开(公告)号：JP2009054154A
公开(公告)日：2009-03-12
申请号：JP2008213366
申请日：2008-08-21
申请人： Picochip Designs Ltd , ピコチップデザインズリミテッド
发明人： CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F7/00 , G06F15/173 , G06F1/32 , G06F9/38 , G06F13/36 , G06F13/38 , G06F15/80
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3287 , G06F9/3824 , G06F9/3885 , G06F15/8007 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： PROBLEM TO BE SOLVED: To reduce the power consumption in a processor architecture. SOLUTION: The processor architecture includes: a plurality of processing elements each of which has at least one input port and at least one output port and has at least a data bus and a valid data signal line; and a bus structure which contains a plurality of switches which are arranged so as to allow the output port of any first processing element to be connected to the input port of any second processing element for a time interval. Each processing element is enabled to set a value on the valid data signal line to a first logic state when the associated data bus contains a transfer value, and to a second logic state when the data bus does not contain a transfer value, and each processing element is further enabled to enter a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：降低处理器架构中的功耗。解决方案：处理器架构包括：多个处理元件，每个处理元件具有至少一个输入端口和至少一个输出端口，并且至少具有数据总线和有效的数据信号线; 以及总线结构，其包含多个开关，其布置成允许任何第一处理元件的输出端口以任何时间间隔连接到任何第二处理元件的输入端口。当相关的数据总线包含转移值时，每个处理元件能够将有效数据信号线上的值设置为第一逻辑状态，并且当数据总线不包含转移值时将其设置为第二逻辑状态，并且每个处理当相关联的输入端口的有效数据信号线上的值处于第二逻辑状态时，元件还能够进入预定时间间隔的等待状态。版权所有（C）2009，JPO＆INPIT

8. 发明专利

AU2003250383A1 PROCESSOR ARRAY 未知
公开(公告)号：AU2003250383A1
公开(公告)日：2004-02-09
申请号：AU2003250383
申请日：2003-06-27
申请人： PICOCHIP DESIGNS LTD
发明人： ROBBINS WILLIAM , DAVIDSON MICHAEL , HOWELL SIMON , CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F15/80 , G06F11/20 , G11C29/00
摘要： An array of processing elements can incorporate a degree of redundancy. Specifically, the array includes one or more spare, or redundant, rows of array elements, in addition to the number required to implement the intended function or functions of the device. If a defect occurs in one of the processors in the device, then the entire row which includes that defective processor is not used, and is replaced by a spare row.

9. 发明专利

GB2370380B Processor architecture 未知
公开(公告)号：GB2370380B
公开(公告)日：2003-12-31
申请号：GB0030993
申请日：2000-12-19
申请人： PICOCHIP DESIGNS LTD
发明人： CLAYDON ANTHONY PETER JOHN , CLAYDON ANNE PATRICIA
IPC分类号： G06F7/00 , G06F15/80 , G06F15/173

10. 发明专利

AU9576801A Processor architecture 未知
公开(公告)号：AU9576801A
公开(公告)日：2002-07-01
申请号：AU9576801
申请日：2001-10-19
申请人： PICOCHIP DESIGNS LTD
发明人： CLAYDON ANTHONY PETER JOHN
IPC分类号： G06F7/00 , G06F1/32 , G06F9/38 , G06F13/36 , G06F15/80 , G06F15/78
摘要： A processor architecture includes a plurality of processing elements and a bus structure. Each element has at least one input port and at least one output port, each port having at least a data bus and a valid data signal line. The bus structure contains a plurality of switches arranged to connect an output port of any first processing element to the input port of any second processing element for a time interval. Each processing element sets a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value and to a second logic state when it does not contain a transfer value. Each processing element enters a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式