专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060190676A1 Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks 有权
公开(公告)号：US20060190676A1
公开(公告)日：2006-08-24
申请号：US11064354
申请日：2005-02-23
申请人： Douglas Butler , Oscar Jones , Michael Parris , Kim Hardee
发明人： Douglas Butler , Oscar Jones , Michael Parris , Kim Hardee
IPC分类号： G06F13/28
CPC分类号： G06F12/0804 , G11C11/406 , G11C11/40607 , G11C11/4076
摘要： A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

2. 发明申请

US20060005053A1 Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices 审中-公开
标题翻译：用于缓存集成电路存储器件的低功耗数据保留待机模式技术中的缓存和标签掉电功能
公开(公告)号：US20060005053A1
公开(公告)日：2006-01-05
申请号：US10881767
申请日：2004-06-30
申请人： Oscar Jones , Douglas Butler , Michael Parris
发明人： Oscar Jones , Douglas Butler , Michael Parris
IPC分类号： G06F1/26
CPC分类号： G06F12/0804 , G06F1/3203 , G06F1/3275 , G06F2212/1028 , G06F2212/3042 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices, in particular cached dynamic random access memory (DRAM) and cached static random access memory (SRAM), wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode. If a DRAM cache is used, the refresh cycles can be inhibited to the DRAM cache, since it has been powered-down, so that additional power savings can be realized during self-refresh power-down standby. When power-down standby is exited, the cache operations are enabled as soon as the cache, tag and control circuitry are powered-up and a clear tag sequence is executed.
摘要翻译：用于缓存的集成电路存储器件（特别是缓存的动态随机存取存储器（DRAM））和高速缓存的静态随机存取存储器（SRAM）的低功率数据保持待机模式技术中的高速缓存和标签掉电功能，其中高速缓存中的数据在输入掉电时，从高速缓存写入主存储器阵列（回写操作），使得高速缓存，标签和大部分高速缓存控制逻辑在掉电待机模式下可以掉电。如果使用DRAM高速缓存，则可以禁止刷新周期到DRAM高速缓存，因为它已经掉电，从而在自刷新掉电待机期间可以实现额外的功率节省。当退出备用电源时，一旦高速缓存，标签和控制电路通电并且执行了清晰的标签序列，就启用高速缓存操作。

3. 发明申请

US20060190678A1 Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag 审中-公开
标题翻译：静态随机存取存储器（SRAM）兼容，高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）与单个DRAM缓存和标签结合的方法
公开(公告)号：US20060190678A1
公开(公告)日：2006-08-24
申请号：US11062974
申请日：2005-02-22
申请人： Douglas Butler , Oscar Jones , Michael Parris
发明人： Douglas Butler , Oscar Jones , Michael Parris
IPC分类号： G06F13/28
CPC分类号： G06F12/0893 , G06F2212/3042 , G11C11/406 , G11C11/40603 , G11C11/40607 , G11C11/40615 , G11C11/40618
摘要： A static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag provides a memory architecture comprising low cost DRAM memory cells that is available for system accesses 100% of the time and is capable of executing refreshes frequently enough to prevent data loss. Any subarray of the memory can be written from cache or refreshed at the same time any other subarray is read or written externally.
摘要翻译：兼容的静态随机存取存储器（SRAM），高可用性存储器阵列和采用同步动态随机存取存储器（DRAM）与单个DRAM高速缓存和标签相结合的方法提供了包括可用于系统访问的低成本DRAM存储器单元的存储器架构 100％的时间，并且能够频繁地执行刷新以防止数据丢失。存储器的任何子阵列可以从高速缓存中写入或刷新，同时任何其他子阵列被外部读取或写入。

4. 发明申请

US20050286291A1 Dual access DRAM 有权
标题翻译：双通道DRAM
公开(公告)号：US20050286291A1
公开(公告)日：2005-12-29
申请号：US10878800
申请日：2004-06-28
申请人： Michael Parris , Oscar Jones , Douglas Butler
发明人： Michael Parris , Oscar Jones , Douglas Butler
IPC分类号： G11C7/10 , G11C11/24 , G11C11/4093
CPC分类号： G11C7/1048 , G11C7/1075 , G11C11/4093 , G11C2207/002
摘要： A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.
摘要翻译：双存取DRAM包括第一和第二组数据线。通过将第二组复用晶体管添加到与现有的多路复用晶体管类似的定时和寻址控制的数据线上，可以通过额外的一组数据线将数据传输到第二子阵列。第二组数据线是除了正常的数据线之外使用的附加内部读/写线。第二组数据线被设计为具有相应低电容的短长度，使得读出放大器上的额外负载较小。

5. 发明授权

US4893272A Ferroelectric retention method 失效
标题翻译：铁电保留法
公开(公告)号：US4893272A
公开(公告)日：1990-01-09
申请号：US184996
申请日：1988-04-22
申请人： S. Sheffield Eaton, Jr. , Douglas Butler , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Douglas Butler , Michael Parris
IPC分类号： G11C11/41 , G11C11/22 , G11C14/00 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22
摘要： Polarization retention of a ferroelectric material in a memory cell is improved by open circuiting the write pulse. The depolarizing field is reduced by allowing charge to dissipate through the ferroelectric material, causing a polarizing field.

6. 发明申请

US20050289293A1 Dual-port DRAM cell with simultaneous access 审中-公开
标题翻译：双端口DRAM单元同时存取
公开(公告)号：US20050289293A1
公开(公告)日：2005-12-29
申请号：US10878802
申请日：2004-06-28
申请人： Michael Parris , Douglas Butler
发明人： Michael Parris , Douglas Butler
IPC分类号： G06F12/00 , G11C8/16 , G11C11/405 , G11C11/406
CPC分类号： G11C11/405 , G11C8/16 , G11C11/406 , G11C11/40603
摘要： A dual-port memory substantially eliminates noise problems associated with the staggered methods of operation. The first and second word lines of a dual-port memory cell are simultaneously activated, such that all four bit lines associated with the cell also move at the same time. The dual-port memory uses simple control logic circuitry without the need for additional external control signals. There are no lock-out times or write restrictions with the method of the present invention. The dual-port memory of the present invention includes a method for hiding refresh, and a method for increasing operating speed.
摘要翻译：双端口存储器基本上消除了与交错操作方法相关联的噪声问题。同时激活双端口存储器单元的第一和第二字线，使得与单元相关联的所有四个位线也同时移动。双端口存储器使用简单的控制逻辑电路，而不需要额外的外部控制信号。通过本发明的方法，没有锁定时间或写入限制。本发明的双端口存储器包括用于隐藏刷新的方法，以及用于提高操作速度的方法。

7. 发明授权

US07199084B2 Concentrated suspensions 有权
标题翻译：浓缩悬浮液
公开(公告)号：US07199084B2
公开(公告)日：2007-04-03
申请号：US10103221
申请日：2002-03-21
申请人： Michael Parris , Geoff Robinson
发明人： Michael Parris , Geoff Robinson
IPC分类号： C09K8/18 , C09K8/20
CPC分类号： C09K8/82 , C09K8/58 , C09K8/62 , C09K8/64
摘要： Suspensions are provided of water-soluble materials in non-aqueous carrier fluids using suspension agents that include thixotropic agents and, optionally, organophilic clays. Methods of forming such suspensions are provided. Methods are also provided for using such suspensions to prepare aqueous solutions, in particular thickened aqueous solutions, in particular for use in oilfield treatments.
摘要翻译：使用包括触变剂和任选的亲有机粘土的悬浮剂在非水载体流体中提供水溶性材料的悬浮液。提供了形成这种悬浮液的方法。还提供了使用这种悬浮液来制备水溶液，特别是增稠的水溶液，特别是用于油田处理的方法。

8. 发明授权

US5763298A Bond pad option for integrated circuits 失效
标题翻译：用于集成电路的焊盘选项
公开(公告)号：US5763298A
公开(公告)日：1998-06-09
申请号：US868179
申请日：1997-06-03
申请人： Michael Parris , Michael V. Cordoba
发明人： Michael Parris , Michael V. Cordoba
IPC分类号： H01L21/60 , H01L23/485 , H01L23/50 , H01L27/118 , H01L2/208
CPC分类号： H01L24/06 , H01L23/50 , H01L24/03 , H01L27/11898 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/85385 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14
摘要： An integrated circuit having a first and second bond pads, a latch circuit, and a voltage lead. Different configurations of the internal circuitry of the integrated circuit are selected by applying the voltage lead either to the first or second bond pads. This result is achieved because the latch circuit, coupled between the first and second bond pads, is capable of inverting the voltage response seen at the first bond pad.
摘要翻译：具有第一和第二接合焊盘，锁存电路和电压引线的集成电路。通过将电压引线施加到第一或第二接合焊盘来选择集成电路的内部电路的不同配置。实现该结果是因为耦合在第一和第二接合焊盘之间的锁存电路能够反转在第一接合焊盘处看到的电压响应。

9. 发明申请

US20060022742A1 Powergating method and apparatus 有权
标题翻译：电源起动方法和装置
公开(公告)号：US20060022742A1
公开(公告)日：2006-02-02
申请号：US10900505
申请日：2004-07-28
申请人： Michael Parris , Kim Hardee
发明人： Michael Parris , Kim Hardee
IPC分类号： H03K17/687
CPC分类号： H03K19/0016
摘要： A powergating circuit includes a P-channel transistor with a source coupled to VCC, a gate for receiving a first boosted or non-boosted powergating control signal, and a drain forming the internal switched VCC power supply. An N-channel transistor has a source coupled to VSS, a gate for receiving a second boosted or non-boosted powergating control signal, and a drain forming the internal switched VSS power supply. The powergating circuit further includes a circuit for forcing the first and second internal power supply voltages to a mid-point reference voltage during the standby mode.
摘要翻译：电源门控电路包括具有耦合到VCC的源极的P沟道晶体管，用于接收第一升压或非升压功率门控控制信号的栅极和形成内部开关VCC电源的漏极。 N沟道晶体管具有耦合到VSS的源极，用于接收第二升压或非升压的功率门控控制信号的栅极以及形成内部开关VSS电源的漏极。电源门电路还包括用于在待机模式期间将第一和第二内部电源电压强制为中点参考电压的电路。

10. 发明授权

US06881709B2 Viscosity reduction of viscoelastic surfactant based fluids 有权
公开(公告)号：US06881709B2
公开(公告)日：2005-04-19
申请号：US09826127
申请日：2001-04-04
申请人： Erik B. Nelson , Bernhard Lungwitz , Keith Dismuke , Mathew Samuel , Golchi Salamat , Trevor Hughes , Jesse Lee , Philip Fletcher , Diankui Fu , Richard Hutchins , Michael Parris , Gary John Tustin
发明人： Erik B. Nelson , Bernhard Lungwitz , Keith Dismuke , Mathew Samuel , Golchi Salamat , Trevor Hughes , Jesse Lee , Philip Fletcher , Diankui Fu , Richard Hutchins , Michael Parris , Gary John Tustin
IPC分类号： C09K8/536 , C09K8/62 , C09K8/72 , C09K8/74 , C09K8/92 , E21B43/26 , C09K3/00
CPC分类号： C09K8/92 , C09K8/536 , C09K8/62 , C09K8/72 , C09K8/74 , C09K2208/26 , Y10S507/921 , Y10S507/922
摘要： Methods and compositions are disclosed for controlled addition of components that decrease the viscosity of the viscoelastic surfactant fluids or for controlled changes in the electrolyte concentration or composition of the viscoelastic surfactant fluids. One aspect of the invention relates to the use of internal breakers with a delayed activation. Another aspect of the invention relates to the use of precursors that release a breaking system such as alcohol by a process such as melting, slow dissolution, reaction with a compound present in the fluid or added to the fluid during or after the step of injecting, rupture of an encapsulating coating and de-adsorption of a breaking agent absorbed into solid particles. In another aspect of the invention, alcohols are included in a pad to reduce the low-shear viscosity and reduce the resistance to flow of the treatment fluids during a desired phase of the treatment.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式