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1. 发明申请

US20090094497A1 DATA INVERSION REGISTER TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY TESTING 有权
标题翻译：用于集成电路存储器测试的数据反相寄存器技术
公开(公告)号：US20090094497A1
公开(公告)日：2009-04-09
申请号：US11868509
申请日：2007-10-07
申请人： Michael C. Parris , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Oscar Frederick Jones, Jr.
IPC分类号： G01R31/28
CPC分类号： G01R31/31713 , G11C29/10 , G11C29/56 , G11C2029/0409
摘要： A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.
摘要翻译：一种用于集成电路存储器测试的数据反转寄存器技术，其中数据输入信号以预定模式选择性地反转，以最大化在测试期间识别故障的可能性。根据本发明的技术，在预定的输入/输出（I / O））数据输入可以被反转以创建对于I / O电路是“最坏情况”的期望的测试图案（诸如数据条纹），或者列条纹是存储器阵列的“最坏情况”。根据本发明的技术的电路然后匹配数据输出路径的模式，反转适当的数据输出以获得预期的测试器数据。这样，测试模式对任何记忆测试仪都是透明的。

2. 发明授权

US06643212B1 Simultaneous function dynamic random access memory device technique 有权
标题翻译：同步功能动态随机存取存储器件技术
公开(公告)号：US06643212B1
公开(公告)日：2003-11-04
申请号：US10125758
申请日：2002-04-18
申请人： Oscar Frederick Jones, Jr. , Michael C. Parris
发明人： Oscar Frederick Jones, Jr. , Michael C. Parris
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1042 , G11C2207/104 , G11C2207/108 , G11C2207/2281 , G11C2207/229
摘要： A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock cycle. The technique of the present invention is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the advantages of the technique are obtained through the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.
摘要翻译：特别适用于DRAM，同步DRAM（“SDRAM”），专用DRAM，嵌入式DRAM，嵌入式SDRAM等的同时功能动态随机存取存储器（“DRAM”）技术，其能够执行“读取”，“写入” ，“活动”和“预充电”命令。本发明的技术特别适用于嵌入式存储器阵列或特殊DRAM，其中DRAM的输入信号的数量不一定受到机械部件封装约束或分量引脚计数的限制。一般来说，该技术的优点是通过使用单独的地址字段（包括用于“读取”和“写入”命令的存储区地址）来获得，并且通过使用高度并行的“高效”命令来分离“活动”和“预充电”命令的存储体地址操作功能。

3. 发明授权

US08281219B2 Error correction code (ECC) circuit test mode 有权
标题翻译：纠错码（ECC）电路测试模式
公开(公告)号：US08281219B2
公开(公告)日：2012-10-02
申请号：US11840203
申请日：2007-08-16
申请人： Michael C. Parris , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Oscar Frederick Jones, Jr.
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/42 , G11C2029/0409 , G11C2029/0411
摘要： An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time.
摘要翻译：用于集成电路存储器的ECC电路和方法允许用户进入测试模式并选择特定位置以迫使任何存储器芯片上的已知故障，无论其是完全功能还是部分功能。额外的电路放置在现有缓冲器和驱动器已经定位的数据路径中，最大限度地减少了实施强制数据故障所需的额外速度损失或面积。在第一种通用方法中，在给定时间将逻辑零强制到所选数据线上。在第二种通用方法中，在给定时间将逻辑1强制到所选择的数据线上。

4. 发明授权

US06732305B2 Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry 有权
标题翻译：用于验证高速嵌入式同步动态随机存取存储器（SDRAM）电路的测试接口
公开(公告)号：US06732305B2
公开(公告)日：2004-05-04
申请号：US09848800
申请日：2001-05-04
申请人： Oscar Frederick Jones, Jr. , Michael C. Parris
发明人： Oscar Frederick Jones, Jr. , Michael C. Parris
IPC分类号： G11C2900
CPC分类号： G11C29/56012 , G11C11/401 , G11C29/48 , G11C2029/0401 , G11C2029/5602
摘要： An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform the testing. The interface allows for the verification of an embedded memory macro design utilizing a test interface which includes the memory macro and separate on-chip test circuitry so that half-rate, narrow word, input signals from a tester can perform all memory macro operations across the breadth of a wide memory macro input/output (“I/O”) architecture. The on-chip test circuitry may also include a synchronizing circuit to minimize skew between the external clock and the data output from the test chip.
摘要翻译：一种集成且不断启用的片上测试接口，用于验证高速嵌入式存储器的功能，例如同步动态随机存取存储器（“SDRAM”），其允许利用现有的，相对较低的速度（并且因此低成本），测试人员进行测试。该接口允许使用包括存储器宏和单独的片上测试电路的测试接口来验证嵌入式存储器宏设计，使得来自测试者的半速率，窄字，输入信号可以执行所有存储器宏操作宽的内存宏输入/输出（“I / O”）架构的宽度。片上测试电路还可以包括同步电路，以最小化外部时钟与从测试芯片输出的数据之间的偏差。

5. 发明授权

US06657461B2 System and method for high speed integrated circuit device testing utilizing a lower speed test environment 有权
标题翻译：利用低速测试环境进行高速集成电路设备测试的系统和方法
公开(公告)号：US06657461B2
公开(公告)日：2003-12-02
申请号：US09815146
申请日：2001-03-22
申请人： Oscar Frederick Jones, Jr. , Michael C. Parris
发明人： Oscar Frederick Jones, Jr. , Michael C. Parris
IPC分类号： G11C1300
CPC分类号： G01R31/31922 , G01R31/318505 , G01R31/318511
摘要： A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2× frequency clock from the 1× frequency external clock signals (two 1× clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.
摘要翻译：在晶圆探针测试期间以集成电路器件的额定速度进行低成本测试的系统和方法，同时可以以较低的速度操作来自器件的输入信号和输出信号。在所公开的示例性实施例中，探针焊盘用于实现特殊测试模式。当使能时，片上时钟发生器使时钟频率倍增。倍频器从1x频率外部时钟信号（两个1x时钟相位在两个时钟之间具有90度相移）产生2x频率时钟。时钟的第一阶段使用器件的CLK输入，第二阶段使用器件的CKE输入。

6. 发明授权

US06622198B2 Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture 失效
标题翻译：先进的，先进先出的集成（FIFO）电路设备架构
公开(公告)号：US06622198B2
公开(公告)日：2003-09-16
申请号：US09815148
申请日：2001-03-22
申请人： Oscar Frederick Jones, Jr.
发明人： Oscar Frederick Jones, Jr.
IPC分类号： G06F1200
CPC分类号： G06F5/10
摘要： A method for loading an integrated circuit FIFO at extremely high operating frequencies includes providing N logical locations, providing N+1 transparent latch stages, and providing N+1 write pointers, wherein two write pointers are contemporaneously enabled during a FIFO load operation. The method can be extended to enable three or more write pointers for even higher frequency operation.
摘要翻译：用于以极高工作频率加载集成电路FIFO的方法包括提供N个逻辑位置，提供N + 1个透明锁存级，并提供N + 1个写指针，其中两个写指针在FIFO加载操作期间同时启用。该方法可以扩展以使三个或更多个写指针用于更高频率的操作。

7. 发明授权

US06289413B1 Cached synchronous DRAM architecture having a mode register programmable cache policy 有权
标题翻译：具有模式寄存器可编程高速缓存策略的缓存同步DRAM架构
公开(公告)号：US06289413B1
公开(公告)日：2001-09-11
申请号：US09360373
申请日：1999-10-15
申请人： Jim L. Rogers , Steven W. Tomashot , David W. Bondurant , Oscar Frederick Jones, Jr. , Kenneth J. Mobley
发明人： Jim L. Rogers , Steven W. Tomashot , David W. Bondurant , Oscar Frederick Jones, Jr. , Kenneth J. Mobley
IPC分类号： G06F1206
CPC分类号： G06F12/0893 , G06F12/0804
摘要： A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data. The row register stores a row of data latched by the sense amplifiers and the select logic gating circuit, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations being performed.
摘要翻译：具有多存储体架构和可编程高速缓存策略的高速缓存的同步动态随机存取存储器（高速缓存的SDRAM）装置包括同步动态随机存取存储器（SDRAM）存储体，同步静态可随机寻址行寄存器，选择逻辑选通电路和模式寄存器，用于在写周期期间以与标准SDRAM的正常操作模式相对应的写传输模式来操作缓存的SDRAM，并且在写周期期间根据备用操作模式在无写传输模式下操作，从而分别在第一和第二缓存策略下运行。 SDRAM包括用于选择存储体阵列中的一行数据的行解码器，用于锁存由行解码器选择的数据行的读出放大器，以及用于选择该行数据的期望列的同步列选择器。行寄存器存储由读出放大器锁存的一行数据，并且设置在读出放大器和行寄存器之间的选择逻辑选通电路根据特定的同步，有选择地将存在于位线上的数据行写入行寄存器执行内存操作。

8. 发明授权

US07962837B2 Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix 有权
标题翻译：通过使用附加校验位来减少汉明码H矩阵中最小加权码数量的方法，用于减少数据块校验位和校正子生成校验位宽度的技术
公开(公告)号：US07962837B2
公开(公告)日：2011-06-14
申请号：US11855070
申请日：2007-09-13
申请人： Oscar Frederick Jones, Jr.
发明人： Oscar Frederick Jones, Jr.
IPC分类号： H03M13/00
CPC分类号： H03M13/19 , H03M13/618 , H03M13/6502 , H03M13/6561
摘要： A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.
摘要翻译：一种用于通过使用附加校验位来减少校验位和校正子生成的校验位宽度以增加汉明码H矩阵中的最小加权码的数量的技术。本发明的技术可以在不添加额外的校正/检测能力的情况下实现，以便减少用于每个校验位/校正子生成的数据位的数量并减小奇偶生成电路的宽度。

9. 发明授权

US07631233B2 Data inversion register technique for integrated circuit memory testing 有权
标题翻译：用于集成电路存储器测试的数据反转寄存器技术
公开(公告)号：US07631233B2
公开(公告)日：2009-12-08
申请号：US11868509
申请日：2007-10-07
申请人： Michael C. Parris , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Oscar Frederick Jones, Jr.
IPC分类号： G11C29/00 , H04L1/00
CPC分类号： G01R31/31713 , G11C29/10 , G11C29/56 , G11C2029/0409
摘要： A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.
摘要翻译：一种用于集成电路存储器测试的数据反转寄存器技术，其中数据输入信号以预定模式选择性地反转，以最大化在测试期间识别故障的可能性。根据本发明的技术，在预定的输入/输出（I / O））数据输入可以被反转以创建对于I / O电路是“最坏情况”的期望的测试图案（诸如数据条纹），或者列条纹是存储器阵列的“最坏情况”。根据本发明的技术的电路然后匹配数据输出路径的模式，反转适当的数据输出以获得预期的测试器数据。这样，测试模式对任何记忆测试仪都是透明的。

10. 发明授权

US07586355B2 Low skew clock distribution tree 有权
标题翻译：低偏移时钟分配树
公开(公告)号：US07586355B2
公开(公告)日：2009-09-08
申请号：US11776371
申请日：2007-07-11
申请人： Michael C. Parris , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Oscar Frederick Jones, Jr.
IPC分类号： H03K3/84
CPC分类号： G06F1/10 , G11C5/063 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093
摘要： A clock distribution tree for an integrated circuit memory includes a set of data drivers, a corresponding set of input buffers coupled to the data drivers, a first clock distribution tree coupled to the data drivers, and a second clock distribution tree coupled to the input buffers, wherein the first and second clock distribution tree are substantially matched and mirrored distribution trees. The line width of the first clock distribution tree is substantially the same as the line width of the second clock distribution tree. The line spacing of the first clock distribution tree is substantially the same as the line spacing of the second clock distribution tree. Numerous topologies for the first and second clock distribution trees can be accommodated, as long as they are matched and mirrored. Valid times for the integrated circuit memory are maximized and data and clock skew is minimized.
摘要翻译：用于集成电路存储器的时钟分配树包括一组数据驱动器，耦合到数据驱动器的相应的输入缓冲器组，耦合到数据驱动器的第一时钟分配树，以及耦合到输入缓冲器的第二时钟分配树，其中所述第一和第二时钟分布树基本匹配并且镜像分布树。第一时钟分配树的线宽基本上与第二时钟分配树的线宽相同。第一时钟分配树的行间距基本上与第二时钟分配树的行间隔相同。只要匹配和镜像，可以容纳第一和第二时钟分配树的许多拓扑。集成电路存储器的有效时间最大化，数据和时钟偏移最小化。

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